OpenFPGA/openfpga_flow/arch/vpr_only_templates
tangxifan f73dfa2bcc bug fixed in k6_n10_40 architecture 2020-06-11 19:31:15 -06:00
..
k4_N4_tileable_40nm.xml fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI 2020-04-15 15:48:33 -06:00
k6_N10_40nm.xml bug fixed in k6_n10_40 architecture 2020-06-11 19:31:15 -06:00
k6_N10_tileable_40nm.xml add tasks for single mode 2020-04-20 12:55:40 -06:00
k6_frac_N10_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_adder_chain_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_adder_chain_mem16K_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_tileable_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_tileable_adder_chain_40nm.xml add test case of BRAM to Travis CI 2020-04-12 14:27:05 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml add test case of BRAM to Travis CI 2020-04-12 14:27:05 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml try to add aib test case. bug found 2020-04-12 14:54:45 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml add io test cases to Travis CI 2020-04-12 15:01:47 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml add io test cases to Travis CI 2020-04-12 15:01:47 -06:00
k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_tileable_adder_register_chain_40nm.xml add register chain and scan chain to Travis CI 2020-04-12 15:28:22 -06:00
k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml add register chain and scan chain to Travis CI 2020-04-12 15:28:22 -06:00
k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml light change on arch file to accelerate mcnc big20 run 2020-04-19 12:03:31 -06:00
k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml add arch file with spy pads 2020-04-22 12:56:09 -06:00
k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml update timing and rename the arch file 2020-04-18 18:39:47 -06:00
k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00