tangxifan 00a485cbeb [test] add missing file		2022-10-17 19:44:25 -07:00
..
bus_group	[Test] Add missing file	2022-02-20 10:59:44 -08:00
custom_fabric_netlist_location/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
explicit_multi_verilog_files/config	[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks	2022-09-20 12:08:24 -07:00
fabric_key	[Test] Bug fix in test cases	2021-10-11 10:28:09 -07:00
fixed_device_support/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
fixed_simulation_settings	[test] add a new test case to validate that .act file is not required when power analysis flow is off	2022-08-01 18:44:47 -07:00
full_testbench	[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp	2022-01-25 16:41:36 -08:00
generate_fabric	[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification	2021-04-11 17:26:27 -06:00
generate_testbench/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
global_tile_ports	[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases	2022-09-29 10:45:27 -07:00
io_constraints	[test] add missing file	2022-10-17 19:44:25 -07:00
k4_series	[test] add repack design constraints files	2022-10-13 11:22:48 -07:00
no_time_stamp	[test] add golden netlists to ensure no cout in gsb	2022-10-01 11:03:13 -07:00
preconfig_testbench	[Test] Update test case by using GPIO with config_done signals	2022-02-24 09:49:34 -08:00
tile_organization	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
verific_test/config	Added 'basic_tests/verific_test' test-case.	2021-11-01 18:20:57 +05:00
write_gsb	[test] add more test cases to validate gsb options	2022-08-29 22:03:06 -07:00
yosys_only/config	Test case for yosys-only flow added	2022-01-14 15:37:47 +05:00