tangxifan 191a3d1c5e [test] update W		2024-07-10 10:01:31 -07:00
..
arch_bitstreams	[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed	2022-09-20 14:14:18 -07:00
benchmarks	[test] typo	2024-07-09 22:54:33 -07:00
docs	…
fabric_keys	[test] deploy new tests	2023-07-08 21:52:16 -07:00
misc	[script] typo	2023-12-12 13:45:23 -08:00
openfpga_arch	[test] fixed a bug	2024-07-08 22:04:40 -07:00
openfpga_cell_library	Merge pull request #864 from yunuseryilmaz18/master	2022-10-30 12:16:21 -07:00
openfpga_shell_scripts	[test] add extra options to route clock rr_graph command in examples	2024-06-28 13:39:41 -07:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
regression_test_scripts	[test] add new tests to validate rst on lut and clk on lut features	2024-07-09 20:24:23 -07:00
scripts	[script] adapt code format for python	2024-04-10 12:58:05 -07:00
tasks	[test] update W	2024-07-10 10:01:31 -07:00
tech	…
vpr_arch	[test] update arch to allow clock access on CLB inputs	2024-07-09 20:59:44 -07:00
.gitignore	…