tangxifan 13f2d33d37 refactored fpga_define.v generation ... Please enter the commit message for your changes. Lines starting		2019-11-05 12:41:43 -07:00
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base	bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!	2019-11-04 18:05:50 -07:00
bitstream	critical bug fixed for bitstream generation for offset truth tables	2019-10-31 20:16:08 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
module_builder	bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!	2019-11-04 18:05:50 -07:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	added Verilog generation for preconfig top module	2019-10-29 13:54:35 -06:00
spice	Rename SCFF to CCFF, configuration chain flip flop	2019-09-26 11:32:57 -06:00
verilog	refactored fpga_define.v generation	2019-11-05 12:41:43 -07:00