Aur??Lien ALACCHI 10866d1852 Correct verilog syntax error in autocheck testbench		2018-12-08 17:40:23 -07:00
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Circuits	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
SRC	Correct verilog syntax error in autocheck testbench	2018-12-08 17:40:23 -07:00
SpiceNetlists	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
VerilogNetlists	Add timing and initialization for simulation	2018-12-04 17:32:09 -07:00
picorv	Changed for the naming	2018-12-08 16:19:38 -07:00
Makefile	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
go.sh	add a section for picorv generation through the flow	2018-12-08 11:33:14 -07:00
picorv.sh	Changed for the naming	2018-12-08 16:19:38 -07:00