tangxifan 38a81e840e [Script] Skip analysis SDC in multi-clock benchmarks		2022-03-20 10:29:27 +08:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[HDL] Fix a typo	2022-02-15 16:09:14 -08:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization	2021-10-11 09:49:22 -07:00
misc	[Script] Support simplified rewriting for Yosys on output verilog	2022-02-18 14:54:39 -08:00
openfpga_arch	[Doc] Update naming convention for openfpga architecture files	2022-03-20 10:22:41 +08:00
openfpga_cell_library	[Test] Update test case by using GPIO with config_done signals	2022-02-24 09:49:34 -08:00
openfpga_shell_scripts	[Script] Skip analysis SDC in multi-clock benchmarks	2022-03-20 10:29:27 +08:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
regression_test_scripts	[Test] Deploy the new test to basic regressioin tests	2022-03-20 10:18:54 +08:00
scripts	[Script] Fix a bug	2022-02-14 23:11:42 -08:00
tasks	[Test] Add a new test case to valid the architecture using 4 clock in different ports	2022-03-20 10:18:00 +08:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Add an example architecture where clock pins are in separated ports	2022-03-20 10:11:27 +08:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00