tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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0425b00af5
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[engine] fixed a bug for frame-based protocols
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2022-09-14 16:41:30 -07:00 |
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tangxifan
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cb89488f76
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[engine] now support a custom list for indexing I/O children in each module
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2022-09-14 15:54:55 -07:00 |
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tangxifan
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36a4da863c
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[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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tangxifan
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2e45a6143b
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[Engine] Fix a critical bug which causes flatten memory tests failed
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2021-09-15 15:11:58 -07:00 |
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tangxifan
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f2aa31ddb1
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[FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank
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2021-09-15 13:45:30 -07:00 |
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tangxifan
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061952b7fa
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[Engine] Bug fix in computing local WLs for GRID/CB/SB
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2021-09-15 11:51:00 -07:00 |
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tangxifan
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26b1e48723
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[Engine] Merge BL/WLs in the Grid/CB/SB modules
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2021-09-15 11:27:55 -07:00 |
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tangxifan
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b787c4e100
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[Engine] Register QL memory bank as a legal protocol
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2021-09-09 15:06:51 -07:00 |
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tangxifan
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5fe9c27600
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[Tool] Remove redundant assertation
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2020-11-09 09:42:39 -07:00 |
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tangxifan
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ba0120bd76
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[Tool] Remove the limitation on requiring Qb ports for CCFF
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2020-11-06 11:10:04 -07:00 |
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tangxifan
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9b0617ffe6
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[Tool] Bug fix for mappable I/O support
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2020-11-04 20:45:51 -07:00 |
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tangxifan
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37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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tangxifan
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987eccf586
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[Tool] Bug fix in multi-region memory bank; Basic test passed
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2020-10-29 16:26:45 -06:00 |
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tangxifan
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448e88645a
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[Tool] Support multiple memory banks in top-level module
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2020-10-29 12:42:03 -06:00 |
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tangxifan
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824b56f14c
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fabric key can now accept instance name only; decoders are no longer part of the key
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2020-07-06 16:42:33 -06:00 |
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tangxifan
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83e26adf90
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add module usage types for future FPGA-SPICE development
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2020-07-04 22:33:54 -06:00 |
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tangxifan
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033c92c365
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precisely reserve memory for child blocks in bitstream manager
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2020-07-03 22:47:21 -06:00 |
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tangxifan
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57e6c84252
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add reserve net sources and sinks to module manager
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2020-06-29 22:49:11 -06:00 |
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tangxifan
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66746f69da
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optimizing memory efficiency by reserving nets in module manager
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2020-06-29 21:27:43 -06:00 |
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tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fa8dfc1fbd
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add configuration protocol ports to top module for memory bank organization
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fbe05963e0
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add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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8298bbff78
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bug fixed in the fabric bitstream for frame-based configurable memories.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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65df309419
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
c696e3d20f
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refine frame-based memory addition to compact the area
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
290dd1a8a6
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add frame decoder builder to all the module graph builder except the top-level
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
8864920460
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add frame-based memory module builder
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
e089b0ef22
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use constant string for inverted port naming
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2020-06-11 19:31:07 -06:00 |
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tangxifan
|
e6c896d583
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now inout must be global port and I/O port so that it will appear in the top-level module
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2020-04-08 16:54:08 -06:00 |
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tangxifan
|
bcb86801fa
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bug fixed in gpio naming for module manager ports
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2020-04-05 17:26:44 -06:00 |
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tangxifan
|
5f4e7dc5d4
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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tangxifan
|
8b583b7917
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debugging spy port builder in module manager
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2020-04-05 16:01:25 -06:00 |
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tangxifan
|
836f722f20
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start supporting global output ports in module manager
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2020-04-05 15:19:46 -06:00 |
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tangxifan
|
c855ab24f5
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put build top module memory connections online
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2020-02-14 11:07:04 -07:00 |
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tangxifan
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f11832b8cf
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |