4 Commits

Author	SHA1	Message	Date
tangxifan	80bb2baae5	start verification and bug fixing	2020-02-28 14:29:01 -07:00
tangxifan	ae899f3b11	bug fixed for clock names	2020-02-27 16:51:55 -07:00
tangxifan	9b769cd8e4	bug fix for using renamed i/o names	2020-02-27 16:37:20 -07:00
tangxifan	25e0583636	add io location map data structure and start porting verilog testbench generator	2020-02-26 17:10:57 -07:00