tangxifan
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19a551e641
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[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
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2021-10-09 16:44:04 -07:00 |
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tangxifan
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39a69e0d88
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[Engine] Upgrading fabric generator to support customizable shift register banks from fabric key and configuration protocols
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2021-10-08 17:58:06 -07:00 |
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tangxifan
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8f5f30792f
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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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2021-10-08 15:25:37 -07:00 |
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tangxifan
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b87b7a99c5
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[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
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2021-09-29 20:21:46 -07:00 |
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tangxifan
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be4c850d2d
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[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
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2021-09-24 12:03:35 -07:00 |
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tangxifan
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7e27c0caf3
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[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
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2021-09-23 16:16:39 -07:00 |
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tangxifan
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ed80d6b3f4
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[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
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2021-09-05 13:23:38 -07:00 |