tangxifan
|
d9d959709c
|
[Doc] Add missing figures
|
2021-09-20 20:31:53 -07:00 |
|
tangxifan
|
3146d2484f
|
[Doc] Update documentation on the WLR definition for circuit model
|
2021-09-20 17:21:33 -07:00 |
|
tangxifan
|
9b40e74e25
|
[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
|
2021-05-24 15:24:50 -06:00 |
|
tangxifan
|
21a18069a1
|
[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
|
2021-05-24 14:50:55 -06:00 |
|
tangxifan
|
b6b98a75b8
|
[Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model;
|
2021-05-24 13:03:40 -06:00 |
|
tangxifan
|
1c4dc9f74b
|
[Doc] Update documentation about the super LUT feature
|
2021-02-10 11:49:59 -07:00 |
|
tangxifan
|
9c5368f912
|
[Doc] Correct bugs in compiling latexpdf
|
2021-02-07 16:17:54 -07:00 |
|
tangxifan
|
226f6b8d6d
|
[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
|
2021-01-04 18:30:04 -07:00 |
|
tangxifan
|
406edeec89
|
[Doc] Typo fix
|
2020-12-04 15:07:02 -07:00 |
|
tangxifan
|
4fe190fa7e
|
[Doc] Bug fix in LUT circuit model documentation
|
2020-12-04 14:44:27 -07:00 |
|
tangxifan
|
cc0114459a
|
[Doc] Enrich examples for LUT circuit models
|
2020-11-26 13:03:12 -07:00 |
|
tangxifan
|
2b9a97729e
|
[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
|
2020-11-23 15:09:47 -07:00 |
|
tangxifan
|
056b7c0c79
|
[Doc] Update documentation about CCFF circuit model examples
|
2020-11-06 12:22:22 -07:00 |
|
tangxifan
|
ccaa697e5a
|
[Documentation] Add links to technical features to examples
|
2020-10-10 22:40:37 -06:00 |
|
tangxifan
|
de07712a3a
|
update documentation about the frame-based configuration protocol
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
c27d77a418
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |