tangxifan
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681e80d4b6
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[Regression tests] update frac_lut test case using more representative benchmarks
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2020-09-17 10:39:22 -06:00 |
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tangxifan
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c40c9f5876
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[Regression test] add test case for no local routing architecture
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2020-09-16 18:05:33 -06:00 |
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tangxifan
|
35d47ee0e7
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[Regression tests] bug fix in the test case for fully connected output crossbar
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2020-09-16 17:33:54 -06:00 |
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tangxifan
|
30fb99095f
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[Regression Tests] Add new test case for fully connected output crossbar
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2020-09-16 17:29:15 -06:00 |
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tangxifan
|
f42411c29e
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[Regression Tests] Add test cases for routing multiplexer design with input/output buffers only
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2020-09-14 16:03:43 -06:00 |
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tangxifan
|
9bf0e772a3
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[Regression Tests]Add a new testcase for routing multiplexer designs without buffers
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2020-09-14 15:45:35 -06:00 |
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tangxifan
|
6c925dcded
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[regression test] Add more tests for thru channels and deploy to CI
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2020-08-19 20:11:37 -06:00 |
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tangxifan
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bf08e1841c
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add new test case using thru channels
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2020-08-19 17:58:34 -06:00 |
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tangxifan
|
cadf29022e
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add README to explain the organization of regression tests
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2020-07-28 13:44:06 -06:00 |
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tangxifan
|
f33422d4d7
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add regression test to track runtime on big fpga devices using practical benchmarks
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2020-07-28 12:38:42 -06:00 |
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tangxifan
|
a156807559
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enrich basic regression tests to cover more critical microbenchmarks
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2020-07-27 19:47:43 -06:00 |
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tangxifan
|
5d83abb2cf
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bug fix in read architecture bitstream and regression tests
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2020-07-27 19:37:05 -06:00 |
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tangxifan
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50cc4dfba3
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classify regression test to dedicated categories
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2020-07-27 17:18:59 -06:00 |
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tangxifan
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5595ee9052
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refine the test case for load external arch bitstream
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2020-07-27 16:53:29 -06:00 |
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tangxifan
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cec6bf0b6f
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add or2 microbenchmark for testing external arch bitstream
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2020-07-27 15:59:03 -06:00 |
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tangxifan
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4174fbf77d
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add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
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2020-07-27 15:54:46 -06:00 |
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tangxifan
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a3eba8acbe
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update task files using the new syntax on SHELL variables
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2020-07-27 15:25:49 -06:00 |
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tangxifan
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c87f6b75b9
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add test case for FPGA-SPICE
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2020-07-24 19:12:35 -06:00 |
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tangxifan
|
020154b0cd
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add depopulate crossbar test case
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2020-07-24 18:06:02 -06:00 |
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tangxifan
|
ca867ea6fa
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add power gate inverter test case (full testbench)
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2020-07-22 20:09:52 -06:00 |
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tangxifan
|
1a1c3885e7
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use k6 n10 in mux designs to speed up CI
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2020-07-22 13:54:09 -06:00 |
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tangxifan
|
95c1fe61e1
|
use k6 n8 in mux design to speed up CI
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2020-07-22 13:49:03 -06:00 |
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tangxifan
|
f754c8af06
|
use k6_n10 architecture to reduce CI runtime
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2020-07-22 13:45:55 -06:00 |
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tangxifan
|
92c3449999
|
bug fix in the regression test due to benchmark changes
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2020-07-22 13:17:05 -06:00 |
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tangxifan
|
05dccadf21
|
bug fix in the testcases using yosys_vpr flow
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2020-07-22 12:44:19 -06:00 |
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tangxifan
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1d36de817f
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adapt generate bitstream testcase to use yosys vpr flow
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2020-07-22 12:24:34 -06:00 |
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tangxifan
|
b96cdbf857
|
adapt preconfig test cases to use yosys_vpr flow
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2020-07-22 12:23:39 -06:00 |
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tangxifan
|
d8804f4ec1
|
deploy yosys_vpr flow to basic regression tests
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2020-07-22 12:21:59 -06:00 |
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tangxifan
|
eb070694b5
|
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
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2020-07-15 17:52:41 -06:00 |
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tangxifan
|
ca90f337a7
|
add fast configuration chain test case
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2020-07-15 11:56:47 -06:00 |
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tangxifan
|
1e6955aaa4
|
rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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tangxifan
|
f9a2bb0490
|
Reorganize task directory
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2020-07-04 19:06:41 -06:00 |
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tangxifan
|
4f8260a7ba
|
remove obselete codes and update regression tests
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2020-07-04 17:31:34 -06:00 |
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tangxifan
|
1c634e4600
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add missing task file for generate bitstream test case
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2020-07-02 17:24:51 -06:00 |
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tangxifan
|
0d81f60fd8
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add new options to openfpga task configuration files
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2020-06-12 19:48:39 -06:00 |
ganeshgore
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559564c333
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-06-12 17:31:14 -06:00 |
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tangxifan
|
2d35848cfa
|
add external key test cases
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2020-06-12 13:11:21 -06:00 |
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tangxifan
|
65b387a589
|
develop test cases for fabric keys
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2020-06-12 11:32:52 -06:00 |
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tangxifan
|
068d9943e7
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update all the templates and regression test cases with simulation settings
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2020-06-11 19:31:16 -06:00 |
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tangxifan
|
1842bf51e1
|
deploy read_openfpga_simulation_setting in CI on a single test case
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2020-06-11 19:31:16 -06:00 |
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tangxifan
|
c87dbc4880
|
start using counter benchmark in regression tests
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
3f9afea3e8
|
add preconfig testbench test case for memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
288294c23a
|
add fast configuration test case for memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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tangxifan
|
73d4c835b7
|
add regression test case for memory bank
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2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
2def059b5b
|
add standalone configuration protocol to pre config test cases
|
2020-06-11 19:31:12 -06:00 |
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tangxifan
|
5f6a790eff
|
add new test cases for the standalone memory configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
a5138113e4
|
add fast configuration testcase
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8b3e79766c
|
add fast configuration option to fpga_verilog to speed up full testbench simulation
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
05aa166a9e
|
add preconfig testbench cases to regression tests for different configuration protocols
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
827e2e6713
|
file moving in regression tests
|
2020-06-11 19:31:11 -06:00 |