tangxifan
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409b3f6896
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add lb_rr_graph builder for the refactored version
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2020-02-17 21:11:56 -07:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
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13fadd0f91
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move compact routing hierarchy to build_fabric command
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2020-02-12 15:49:47 -07:00 |
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tangxifan
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175bef014a
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add compact_routing hierarchy command
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2020-02-11 17:40:37 -07:00 |
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tangxifan
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ed9e038845
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add functionality of LUT truth table fix-up
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2020-02-06 17:14:29 -07:00 |
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tangxifan
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dad204674b
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done an initial version of clustering net fix-up based on routing results. Debugging on the way
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2020-02-05 21:50:52 -07:00 |
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tangxifan
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5006a4395d
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bring RRGraph object and writer online
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2020-01-31 16:39:40 -07:00 |
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tangxifan
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02d6256e95
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pass simple test on pb_type annotation for frac_lut5 architecture
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2020-01-30 21:39:44 -07:00 |
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tangxifan
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568ed120c2
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change report naming fix-up to be XML format
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2020-01-29 21:53:56 -07:00 |
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tangxifan
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2dc4c26257
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add naming fix-up
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2020-01-29 17:49:33 -07:00 |
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tangxifan
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8c86c0af04
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add check netlist naming conflict command and functions
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2020-01-29 16:23:41 -07:00 |
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tangxifan
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bb7fa2af77
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add pb interconnect binding to circuit model
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2020-01-28 17:04:10 -07:00 |
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tangxifan
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5ecb771673
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debugging the annotation to physical mode of pb_types
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2020-01-27 17:43:22 -07:00 |
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tangxifan
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2e41138633
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use a micro benchmark for vpr quick-run
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2020-01-26 17:56:22 -07:00 |
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tangxifan
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93ab4b8dd2
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add test case for openfpga shell
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2020-01-26 17:30:46 -07:00 |