AurelienUoU
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056219f180
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Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
tangxifan
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5a40c6713d
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managed to plug in refactored essential gates, dead codes to be removed
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2019-08-21 21:50:26 -06:00 |
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tangxifan
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29104b6fa5
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rework on the circuit model ports and start prototyping mux Verilog generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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a7ac1e4980
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remame methods in circuit_library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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c7526cb43c
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memory sanitized
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2019-08-13 14:19:40 -06:00 |
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tangxifan
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392f579836
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add linking functions for circuit models and architecture, memory sanitizing is ongoing
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2019-08-13 13:25:23 -06:00 |
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tangxifan
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c56f289d3e
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add checkers for circuit library
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2019-08-12 16:45:33 -06:00 |
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tangxifan
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d4ae160d3a
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start adding circuit library checkers
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2019-08-12 14:20:11 -06:00 |
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tangxifan
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c8d04c4f00
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plug in fast look-up builder
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2019-08-08 21:20:28 -06:00 |
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tangxifan
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158c67075e
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built a conversion from spice_models to circuit_library and plug in
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2019-08-08 17:25:27 -06:00 |
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tangxifan
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fb2ca66ce9
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start adding submodules of local encoders to multiplexer
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2019-08-06 14:17:55 -06:00 |
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tangxifan
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33f3a991b5
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init effort to start developing mux local encoders
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2019-08-06 14:17:55 -06:00 |
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tangxifan
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6e1d49d74e
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start to support direct mapping to MUX2 standard cells
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2019-07-17 07:54:23 -06:00 |
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AurelienUoU
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19ccbce9d0
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Rename option to use circuit_model rather than spice_model
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2019-07-12 16:18:28 -06:00 |
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tangxifan
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f43955037c
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remove input port requirements for SRAM circuit module
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2019-06-10 15:29:44 -06:00 |
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tangxifan
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5a97e3e602
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update Makefile t
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2019-05-03 11:48:41 -06:00 |