tangxifan
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81171a8f97
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start transplanting FPGA-SPICE
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2020-07-05 12:10:12 -06:00 |
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tangxifan
|
f97e3bfba6
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add timer to openfpga shell
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2020-07-02 18:02:33 -06:00 |
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tangxifan
|
5a04da2082
|
fix memory leakage in openfpga title
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2020-04-07 16:14:41 -06:00 |
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tangxifan
|
637be076dc
|
adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working
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2020-03-21 18:49:20 -06:00 |
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tangxifan
|
092e10afda
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bring pnr sdc generator online and fixed minor bugs in bitstream writing
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2020-02-28 11:14:50 -07:00 |
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tangxifan
|
8e97443410
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start working on repack
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2020-02-17 17:57:43 -07:00 |
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tangxifan
|
8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
|
cdb3b6de46
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add read_openfpga_arch to OpenFPGA shell
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2020-01-23 19:10:53 -07:00 |
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tangxifan
|
3cb16a2279
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move basic commands to separated CXX files
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2020-01-23 14:42:49 -07:00 |
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tangxifan
|
ba207ee5a5
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start split workload from the main.cpp in openfpga
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2020-01-23 13:24:35 -07:00 |
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tangxifan
|
7909a1ad82
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update title for openfpga shell
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2020-01-22 20:29:57 -07:00 |
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tangxifan
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523f9ac391
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start implement openfpga shell and use vpr as a macro
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2020-01-22 20:20:10 -07:00 |