4 Commits

Author	SHA1	Message	Date
tangxifan	3f1fb70d16	FPGA SDC now constrain max and min delay for primitive modules in grids	2020-04-21 11:00:28 -06:00
tangxifan	329b0a9cf1	add options to enable SDC constraints on zero-delay paths	2020-03-25 15:55:30 -06:00
tangxifan	092e10afda	bring pnr sdc generator online and fixed minor bugs in bitstream writing	2020-02-28 11:14:50 -07:00
tangxifan	fdcb982903	adapt pnr sdc grid writer	2020-02-27 21:06:33 -07:00