tangxifan
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ca593f23fc
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[Test] Merge reg test to build tests on Github Actions
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2020-11-24 15:32:45 -07:00 |
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tangxifan
|
27e68f1ea2
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[Test] Add check ccache size
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2020-11-24 15:20:38 -07:00 |
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tangxifan
|
955e49dca1
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[Test] bug fix for ccache and enhance printing messages
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2020-11-24 15:10:33 -07:00 |
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tangxifan
|
54db85c2f6
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[Test] Correct the path to test scripts
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2020-11-24 14:27:40 -07:00 |
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tangxifan
|
8bbbec37a3
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[Doc] Add badges for Github Actions to frontpage README
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2020-11-24 13:56:01 -07:00 |
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tangxifan
|
03f18b776c
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[Test] typo fix
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2020-11-24 13:44:14 -07:00 |
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tangxifan
|
5210eae960
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[Test] Simplify syntax and avoid complex if logics
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2020-11-24 13:41:47 -07:00 |
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tangxifan
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68827a53b6
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[Test] Bug fix in wrong paths to call regression test scripts
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2020-11-24 12:37:42 -07:00 |
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tangxifan
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87f2fa7a90
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[Test] Use if in run blocks
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2020-11-24 11:30:20 -07:00 |
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tangxifan
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5b9c0886e9
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[Test] Keep fixing the if syntax error
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2020-11-24 11:23:54 -07:00 |
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tangxifan
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abafeb01a8
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[Test] Rename test yml and try to patch if errors
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2020-11-24 11:20:40 -07:00 |
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tangxifan
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6ee5fce61f
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[Test] Fix if syntax errors
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2020-11-24 11:11:34 -07:00 |
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tangxifan
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a6e55cbe94
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[Test] Try to fix the syntax error in if clauses
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2020-11-24 11:07:10 -07:00 |
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tangxifan
|
5574c7b440
|
[Test] Add regression tests to Github Actions
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2020-11-24 11:03:31 -07:00 |
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tangxifan
|
04d84a12b5
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[Test] Rename build tests
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2020-11-24 10:43:17 -07:00 |
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tangxifan
|
6b9f236d81
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[Test] Specify paths to ccache files
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2020-11-24 10:37:15 -07:00 |
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tangxifan
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43564c584d
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[Test] Add the matrix for compiler compatibility tests
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2020-11-24 10:29:05 -07:00 |
|
tangxifan
|
0daa484134
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[Test] Remove wrong syntax about ccache
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2020-11-24 10:25:12 -07:00 |
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tangxifan
|
0bb185f6a0
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[Test] Try to fix the problem on storing ccache results
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2020-11-24 10:16:24 -07:00 |
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tangxifan
|
3536f0baae
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[Test] Adapt regression tests scripts for github actions
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2020-11-24 09:58:23 -07:00 |
|
tangxifan
|
dc164a0636
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[Test] Remove unnecssary space that break CI
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2020-11-24 09:38:18 -07:00 |
|
tangxifan
|
c257abe864
|
[Test] Add CMake and iVerilog version number output
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2020-11-24 09:33:00 -07:00 |
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tangxifan
|
121f628f6b
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[Test] Add CXX and CC configuration
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2020-11-24 09:31:25 -07:00 |
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tangxifan
|
82954483b8
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[Test] Bug fix in using MAKEFLAGS
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2020-11-24 09:29:11 -07:00 |
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tangxifan
|
88bf523bc8
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[Test] Remove artifact uploading; focus on testing ccache
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2020-11-24 09:19:09 -07:00 |
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tangxifan
|
f417996b36
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[Test] Add ccache to dependency
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2020-11-23 22:57:19 -07:00 |
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tangxifan
|
4d2f6bc656
|
[Test] Bug fix
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2020-11-23 22:52:01 -07:00 |
|
tangxifan
|
703ba0b174
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[Test] Enable ccache in cmake execution
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2020-11-23 22:46:20 -07:00 |
|
tangxifan
|
814aa49a5b
|
[Test] Bug fix in github Actions script
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2020-11-23 22:34:37 -07:00 |
|
tangxifan
|
6dbf22bc3d
|
[Test] Add artifact upload
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2020-11-23 22:32:28 -07:00 |
|
tangxifan
|
d3e2dee215
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[Test] Bug fix in github action script
|
2020-11-23 22:31:30 -07:00 |
|
tangxifan
|
433c259d91
|
[Test] Add ccache for compilation results to speed up CI
|
2020-11-23 22:28:17 -07:00 |
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tangxifan
|
af21aa0522
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[Test]Try env variable for parallel cmake build
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2020-11-23 20:52:07 -07:00 |
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tangxifan
|
7bd2622fd6
|
[Test] Try parallel build for Cmake in github actions
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2020-11-23 20:50:19 -07:00 |
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tangxifan
|
84c39315a5
|
[Test] Use example CMake build scripts from Github actions
|
2020-11-23 20:40:05 -07:00 |
|
tangxifan
|
de44e8c9d1
|
[Test] Bug fix for github actions
|
2020-11-23 20:24:18 -07:00 |
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tangxifan
|
a95ddef90d
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[Test] Bug fix in calling scripts for Github Actions
|
2020-11-23 20:22:59 -07:00 |
|
tangxifan
|
f2b6655550
|
[Test] Start porting to Github Actions with build test
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2020-11-23 20:19:44 -07:00 |
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tangxifan
|
6ba02f35ca
|
Merge pull request #130 from antmicro/rr_graph_load_fix
Fix for rr graph loading by VPR
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2020-11-23 09:31:29 -07:00 |
Maciej Kurc
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3d38e76c8f
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Disabled printing segment ids for non-channel nodes.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
|
2020-11-23 17:07:28 +01:00 |
|
Maciej Kurc
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b6728cf2d9
|
Added loading rr node segment indices
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
|
2020-11-23 14:53:50 +01:00 |
Laboratory for Nano Integrated Systems (LNIS)
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b78803a6bb
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Merge pull request #129 from LNIS-Projects/dev
Generate Signal Initialization in Verilog Testbenches rather than HDL netlists
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2020-11-22 21:48:22 -07:00 |
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tangxifan
|
fd80cacaa3
|
[Flow] Add example script for behaviorial verilog generation
|
2020-11-22 21:14:10 -07:00 |
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tangxifan
|
617f7e3062
|
[Flow] disable signal initialization for behavioral verilog generation
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2020-11-22 21:13:22 -07:00 |
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tangxifan
|
5eb04e6fff
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[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
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2020-11-22 20:53:32 -07:00 |
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tangxifan
|
fd0e6814ea
|
[Doc] Update documentation about the pre-processing flags
|
2020-11-22 20:33:15 -07:00 |
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tangxifan
|
3b2a4c5387
|
[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
|
2020-11-22 20:25:03 -07:00 |
|
tangxifan
|
655da9f3d0
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
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tangxifan
|
348872f8a4
|
[Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes
|
2020-11-22 16:12:28 -07:00 |
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tangxifan
|
57a24570f5
|
[Tool] Move icarus and signal initialization options to testbench generator
|
2020-11-22 16:01:31 -07:00 |