Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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370e3fef83
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[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
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2021-10-30 18:03:59 -07:00 |
ANDREW HARRIS POND
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006b54c4bc
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ready for merge
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2021-07-01 15:35:39 -06:00 |
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ANDREW HARRIS POND
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2567fbee05
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ready to merge
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2021-07-01 15:28:59 -06:00 |
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ANDREW HARRIS POND
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db9231c225
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tests failing with initial blocks
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2021-07-01 13:52:28 -06:00 |
Andrew Pond
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3cfc42cdf9
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added testbench CI
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2021-06-15 14:16:31 -06:00 |