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OpenFPGA
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4922 Commits

Author SHA1 Message Date
tangxifan f13a1a3dee
Merge pull request #530 from lnis-uofu/counters 
Fixed a bug in task run when removing previous runs
 2022-02-15 09:29:01 -08:00
dependabot[bot] 7de269def3
Bump yosys-plugins from `3b18b54` to `ea7411a` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `3b18b54` to `ea7411a`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](3b18b5495c...ea7411a915)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-02-15 07:28:21 +00:00
tangxifan 23e04824fa
Merge branch 'master' into counters 2022-02-14 23:19:56 -08:00
tangxifan 74045fc7a1 [Script] Fix a bug 2022-02-14 23:11:42 -08:00
tangxifan 2990eb7406 [Script] Fixed a bug in task run when removing previous runs 2022-02-14 22:54:16 -08:00
tangxifan 1e8deae120
Merge pull request #529 from lnis-uofu/counters 
Enable comprehensive tests for counter benchmarks
 2022-02-14 18:27:20 -08:00
tangxifan be8f18310d [FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances 2022-02-14 17:16:26 -08:00
tangxifan d3f68db228 [FPGA-Verilog] fixing bugs in reset ports for counters in full testbenches 2022-02-14 17:00:54 -08:00
tangxifan d0fe8d96fa [Test] Update template scripts and assoicated test cases by offering more options 2022-02-14 16:03:48 -08:00
tangxifan d667102a43 [Test] Add new test case to regression tests 2022-02-14 15:58:53 -08:00
tangxifan 70363effa4 [Test] Add a new test to validate 8-bit counters using full testbenches 2022-02-14 15:57:55 -08:00
tangxifan 2fb1df11bb [Script] Add a new example script 2022-02-14 15:54:07 -08:00
tangxifan 7ef808cbe4 [Test] Update pin constraints for different counter benchmarks 2022-02-14 15:28:03 -08:00
tangxifan 34e192c5ca [FPGA-Verilog] Fixed a bug on wiring FPGA global ports 2022-02-14 15:21:29 -08:00
tangxifan 570c1b10dc [Test] Add dedicated pin constraints for counter designs 2022-02-14 13:54:48 -08:00
tangxifan 85011824e2 [Test] Enable Verilog-to-Verification flow for counter8 benchmarks 2022-02-14 13:15:55 -08:00
tangxifan 6630c17c23 [Test] Use preconfigured testbench template to run counter8 tests 2022-02-14 13:07:31 -08:00
tangxifan da3f9ccb80 [Test] Truncating counter designs in each task 2022-02-14 12:22:19 -08:00
tangxifan 0268814fc6 [Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests 2022-02-14 12:20:56 -08:00
tangxifan a80b2d7882
Merge pull request #528 from lnis-uofu/tb 
Now the shared input ports in top-level testbench has a dedicated postfix (except clock ports)
 2022-02-14 12:17:38 -08:00
tangxifan 8d48492ec0 [FPGA-Verilog] Add clock ports to the white list when adding postfix 2022-02-14 11:09:00 -08:00
tangxifan 5794561f7b [FPGA-Verilog] Now shared input wire/register has a postfix in full testbench 2022-02-14 10:39:27 -08:00
tangxifan ae5d77b7bc
Merge pull request #527 from lnis-uofu/dependabot/submodules/yosys-plugins-3b18b54 
Bump yosys-plugins from `13520da` to `3b18b54`
 2022-02-14 09:46:21 -08:00
dependabot[bot] bf9ebccb20
Bump yosys-plugins from `13520da` to `3b18b54` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `13520da` to `3b18b54`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](13520dac01...3b18b5495c)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-02-14 07:25:30 +00:00
tangxifan c58cadafce
Merge pull request #526 from lnis-uofu/tb 
Now preconfigured top-level module has the same port name as reference benchmarks
 2022-02-13 23:01:27 -08:00
tangxifan 2ca73d79e4 [FPGA-Verilog] Fixed the bug on pin constraints 2022-02-13 22:08:06 -08:00
tangxifan b1377f0d34 [FPGA-Verilog] Fix syntax errors 2022-02-13 20:29:05 -08:00
tangxifan 6e132aace4 [FPGA-Verilog] Remove the prefix added by VPR in preconfigured top module 2022-02-13 20:26:21 -08:00
tangxifan fb4106de19 [FPGA-Verilog] Fixed a bug in naming mismatch 2022-02-13 20:06:35 -08:00
tangxifan a068237082 [FPGA-Verilog] Rename internal wire names in testbenches, in order to be consistent with reference benchmarks 2022-02-13 19:55:16 -08:00
tangxifan 4703753807
Merge pull request #524 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-02-12 17:26:11 -08:00
github-actions[bot] c7ae23d9fb Updated Patch Count 2022-02-13 00:23:36 +00:00
tangxifan 9165e9fff6
Merge pull request #521 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-02-11 17:00:24 -08:00
tangxifan 1d1c8e885a
Merge pull request #522 from lnis-uofu/dependabot/submodules/yosys-plugins-13520da 
Bump yosys-plugins from `8bf72c3` to `13520da`
 2022-02-11 11:00:15 -08:00
dependabot[bot] 7f2d0f0e77
Bump yosys-plugins from `8bf72c3` to `13520da` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `8bf72c3` to `13520da`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](8bf72c311a...13520dac01)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-02-11 07:37:50 +00:00
github-actions[bot] 34cb2fe0a4 Updated Patch Count 2022-02-11 00:21:14 +00:00
tangxifan 0581ff8585
Merge pull request #520 from lnis-uofu/dependabot/submodules/yosys-plugins-8bf72c3 
Bump yosys-plugins from `f184835` to `8bf72c3`
 2022-02-09 16:29:40 -08:00
dependabot[bot] 1f19392db1
Bump yosys-plugins from `f184835` to `8bf72c3` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `f184835` to `8bf72c3`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](f184835322...8bf72c311a)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-02-09 07:22:28 +00:00
tangxifan d151a42f12
Merge pull request #519 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-02-07 16:25:54 -08:00
github-actions[bot] 58a53f9a33 Updated Patch Count 2022-02-08 00:23:12 +00:00
tangxifan 6d6849dad7
Merge pull request #517 from lnis-uofu/dependabot/submodules/yosys-plugins-f184835 
Bump yosys-plugins from `d7ec931` to `f184835`
 2022-02-07 09:29:43 -08:00
dependabot[bot] 87466c04cb
Bump yosys-plugins from `d7ec931` to `f184835` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `d7ec931` to `f184835`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](d7ec93162a...f184835322)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-02-07 07:24:38 +00:00
tangxifan 92ede44828
Merge pull request #514 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-02-02 21:31:49 -08:00
github-actions[bot] a7d7b6389d Updated Patch Count 2022-02-03 00:20:34 +00:00
tangxifan d9bb1f23aa
Merge pull request #513 from lnis-uofu/dependabot/submodules/yosys-plugins-d7ec931 
Bump yosys-plugins from `003c697` to `d7ec931`
 2022-02-02 11:21:19 -08:00
dependabot[bot] dbd1bb51b6
Bump yosys-plugins from `003c697` to `d7ec931` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `003c697` to `d7ec931`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](003c697169...d7ec93162a)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-02-02 07:21:19 +00:00
tangxifan f9a067551f
Merge pull request #512 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-02-01 16:29:43 -08:00
github-actions[bot] 32319f7efc Updated Patch Count 2022-02-02 00:21:57 +00:00
tangxifan 9b3560baca
Merge pull request #511 from lnis-uofu/verilog_rel_path 
Now Verilog Testbench Generator has a new option ``--use_relative_path``
 2022-02-01 15:20:54 -08:00
tangxifan 1d3c9ff192 [Script] Adapt python scripts to support include directory 2022-02-01 13:55:25 -08:00