4 Commits

Author	SHA1	Message	Date
tangxifan	7fcd27e000	now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer	2020-03-03 12:29:58 -07:00
tangxifan	e37ac8a098	add grid module Verilog writer	2020-02-16 16:04:41 -07:00
tangxifan	072965cd64	make grid module builder online; basic support on physical tiles	2020-02-13 15:27:16 -07:00
tangxifan	f11832b8cf	start integrating module graph builder	2020-02-12 17:53:23 -07:00