tangxifan
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5eb04e6fff
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[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
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2020-11-22 20:53:32 -07:00 |
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tangxifan
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1a79a55646
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[HDL] Add DFF cell with reset but only 1 output
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2020-11-06 11:19:19 -07:00 |
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tangxifan
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7d46b35296
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[HDL] Add single-output DFF HDL
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2020-11-06 10:18:37 -07:00 |
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tangxifan
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c074e88dcd
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[HDL] Add embedded I/O HDL for Caravel SoC interface
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2020-11-04 17:09:59 -07:00 |
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tangxifan
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c036c87d6d
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[HDL] Bug fix in the GP output pad
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2020-11-02 18:37:53 -07:00 |
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tangxifan
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7e9e0ec9d4
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[HDL] Bug fix in I/O HDL code
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2020-11-02 15:15:45 -07:00 |
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tangxifan
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2f237a6240
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[HDL] Add HDL codes for embedded I/Os
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2020-11-02 14:01:27 -07:00 |
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tangxifan
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019208ec0f
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |