tangxifan
|
a6186db315
|
[Test] Update bitstream annotation with new syntax
|
2021-03-10 20:45:17 -07:00 |
|
tangxifan
|
7d07f5d8cb
|
[Test] Update bitstream setting example with mode bit overwriting
|
2021-03-10 15:34:53 -07:00 |
|
tangxifan
|
d21909ad6c
|
[Test] Use custom rewriting script in lut_adder test
|
2021-03-10 13:48:20 -07:00 |
|
tangxifan
|
37aa42d305
|
[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
|
2021-03-08 21:38:51 -07:00 |
Lalit Sharma
|
7945628307
|
Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification
|
2021-03-07 22:25:01 -08:00 |
|
tangxifan
|
0d82e4939c
|
[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
|
2021-02-26 09:35:40 -07:00 |
|
tangxifan
|
a62786986b
|
[Test] Turn off verification in adder lut test temporarily
|
2021-02-23 19:03:25 -07:00 |
|
tangxifan
|
53df7f69e7
|
[Test] Bug fix in the test case using lut adder
|
2021-02-23 16:59:46 -07:00 |
|
tangxifan
|
db71cc8a16
|
[Test] Add LUT adder test using quicklogic synthesis script
|
2021-02-23 16:50:58 -07:00 |