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OpenFPGA
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2 Commits

Author SHA1 Message Date
tangxifan 15e26a5602 [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
tangxifan 3efd1a2a6d print verilog module writer online 2020-02-16 12:04:03 -07:00