6 Commits

Author	SHA1	Message	Date
tangxifan	e37ac8a098	add grid module Verilog writer	2020-02-16 16:04:41 -07:00
tangxifan	c20caa1fa3	routing module Verilog writer is online	2020-02-16 14:47:54 -07:00
tangxifan	105ccabecc	adapt memroy writer for verilog	2020-02-16 12:41:43 -07:00
tangxifan	c9d8120ae0	adapt Verilog mux writer	2020-02-16 12:35:41 -07:00
tangxifan	4cb61e2138	bring preprocessing flag Verilog netlists online	2020-02-16 00:03:24 -07:00
tangxifan	622c7826d1	start transplanting fpga_verilog	2020-02-15 15:03:00 -07:00