tangxifan
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4083fae41a
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add new test cases about user-defined simulation settings
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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2fbf9c2cfc
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change to a higher simulation clock speed to accelerate CI verification.
Later, we should place simulation information in another XML so that we can reuse that easily
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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889bc8dbe8
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add more test cases about LUT design and deploy to CI
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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889f179ce7
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add local encoder test case
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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73e9006372
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add arch file with spy pads
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2020-04-22 12:56:09 -06:00 |
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tangxifan
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f6b7583a2a
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add tasks for single mode
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2020-04-20 12:55:40 -06:00 |
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tangxifan
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f76a3090c4
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add mcnc big20 test cases and start debugging
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2020-04-18 19:25:16 -06:00 |
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tangxifan
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2ffd174e6a
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
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tangxifan
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23aef96d3a
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add behavioral verilog test case to Travis CI
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2020-04-12 19:55:47 -06:00 |
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tangxifan
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f71a85a1d4
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add test cases on different routing multiplexer circuit designs to Travis CI
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2020-04-12 15:39:45 -06:00 |
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tangxifan
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214d98fbcd
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add register chain and scan chain to Travis CI
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2020-04-12 15:28:22 -06:00 |
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tangxifan
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da5af8f0e0
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try to add aib test case. bug found
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2020-04-12 14:54:45 -06:00 |
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tangxifan
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600a48edc7
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add test case of BRAM to Travis CI
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2020-04-12 14:27:05 -06:00 |
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tangxifan
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49ddbf98c3
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add more testing architecture to openfpga_flow
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2020-04-11 18:01:09 -06:00 |
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tangxifan
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130b78ca74
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update arch in openfpga_flow
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2020-04-11 18:00:37 -06:00 |
ganeshgore
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eb3b02277a
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Added XML and benchmarks for testing
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2020-04-06 00:32:06 -06:00 |