4 Commits

Author	SHA1	Message	Date
tangxifan	078f72320f	debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports	2020-02-27 13:24:26 -07:00
tangxifan	f558405887	ported verilog testbench generator online. Split from fabric generator. Testing to be done	2020-02-27 12:33:09 -07:00
tangxifan	c6c3ef71f3	adapt all the Verilog submodule writers and bring it onlien	2020-02-16 13:35:18 -07:00
tangxifan	8b0df8632c	bring fpga verilog create directory online	2020-02-15 20:38:45 -07:00