riscv
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OpenFPGA
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3 Commits

Author SHA1 Message Date
tangxifan baa2c6b7ef update arch to support reset signal for SRAm 2020-06-11 19:31:14 -06:00
tangxifan 82b04ae3f0 add SRAM verilog for memory bank usage 2020-06-11 19:31:14 -06:00
Ganesh Gore 7bfc48b8e4 Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00