Commit Graph

12 Commits

Author SHA1 Message Date
tangxifan 8cc72536d1 minor bug fixing 2019-11-22 15:54:14 -07:00
tangxifan a308a13d7c use prefix instead of lib_name when building modules, then use lib_name for standard cell modules 2019-11-05 15:41:59 -07:00
tangxifan 358e9892ac reduce some error message to warnings 2019-11-02 00:09:13 -06:00
tangxifan 7c116aac2f added Verilog generation for preconfig top module 2019-10-29 13:54:35 -06:00
AurelienUoU 056219f180 Rename SCFF to CCFF, configuration chain flip flop 2019-09-26 11:32:57 -06:00
tangxifan 0399319212 refactored LUT Verilog generation 2019-09-11 17:04:43 -06:00
tangxifan 732e24767f developing module manager 2019-08-22 23:49:35 -06:00
tangxifan 5f55fc7b49 add missing files and developing essential gates 2019-08-20 20:43:46 -06:00
tangxifan 29104b6fa5 rework on the circuit model ports and start prototyping mux Verilog generation 2019-08-20 15:24:53 -06:00
tangxifan a7ac1e4980 remame methods in circuit_library 2019-08-20 15:24:53 -06:00
tangxifan c7526cb43c memory sanitized 2019-08-13 14:19:40 -06:00
tangxifan ef4d15df4e reorganize the libarchfpga repository 2019-08-13 13:37:35 -06:00