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OpenFPGA
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4 Commits

Author SHA1 Message Date
tangxifan 8f0ae937bc [Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank 2021-09-29 16:57:49 -07:00
tangxifan 7723e00e6c [Engine] Adding the function that builds a shift register module for BL/WLs 2021-09-28 22:49:24 -07:00
tangxifan 8864920460 add frame-based memory module builder 2020-06-11 19:31:09 -06:00
tangxifan 002c2795fe add memory module builder 2020-02-12 20:06:38 -07:00