tangxifan
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7b9384f3b2
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add write_gsb command to shell interface
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2020-03-21 19:40:26 -06:00 |
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tangxifan
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637be076dc
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adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working
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2020-03-21 18:49:20 -06:00 |
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tangxifan
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9a518e8bb6
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bug fixed for tileable rr_graph builder for more 4x4 fabrics
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2020-03-21 18:07:00 -06:00 |
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tangxifan
|
63c4669dbb
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fixed bug in the fast look-up for tileable rr_graph
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2020-03-21 17:36:08 -06:00 |
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tangxifan
|
c0e8d98c6f
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bug fixed in tile direct builder
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2020-03-21 12:43:56 -06:00 |
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tangxifan
|
8f35f191eb
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use the formalized function in FPGA-SDC to identify direct connection
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2020-03-21 11:42:00 -06:00 |
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tangxifan
|
28123b8052
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remove the direct connected IPIN/OPIN from RR GSB builder
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2020-03-21 11:38:39 -06:00 |
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tangxifan
|
2ff2d65e58
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start debugging tileable routing using larger array size. Bug spotted in finding chan nodes
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2020-03-20 22:12:23 -06:00 |
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tangxifan
|
682b667a3c
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minor bug fix for direct connection in FPGA-SDC
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2020-03-20 21:44:01 -06:00 |
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tangxifan
|
05ec86430a
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temp fix for direct connections. Should notify VPR team about this issue: delayless switch is used in direct connection but it is considered as configurable....which is actually NOT!
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2020-03-20 17:56:03 -06:00 |
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tangxifan
|
3c37b33f17
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critical bug fixed in edge sorting for rr_gsb
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2020-03-20 17:45:50 -06:00 |
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tangxifan
|
060c1a41d9
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critical bug fixed for tileable routing: delayless and wire2ipin switch was reverted
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2020-03-20 17:23:19 -06:00 |
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tangxifan
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2c0c5a061b
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spot a bug in assigning rr_switch in tileable routing
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2020-03-20 16:53:43 -06:00 |
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tangxifan
|
708fda9606
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fixed a bug in using tileable routing when directlist is enabled
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2020-03-20 16:38:58 -06:00 |
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tangxifan
|
c5049a1ec8
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keep debugging tile direct connections
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2020-03-20 15:10:00 -06:00 |
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tangxifan
|
a46fc9f028
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add debugging information for tile direct builder
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2020-03-20 14:59:46 -06:00 |
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tangxifan
|
9837be618d
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start debugging tile direct with micro architecture
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2020-03-20 14:52:52 -06:00 |
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tangxifan
|
a0b150f12e
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adding micro architecture using adder chain
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2020-03-20 14:18:59 -06:00 |
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tangxifan
|
8d57808d07
|
add missing files for micro benchmarks
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2020-03-20 11:08:55 -06:00 |
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tangxifan
|
3647548526
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clean up on the shell echo commands
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2020-03-20 11:07:45 -06:00 |
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tangxifan
|
808853db0b
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critical bug fixed for find proper pb_route traceback
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2020-03-13 12:26:37 -06:00 |
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tangxifan
|
81e5af464e
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improve lb_route to avoid routing combinational loops
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2020-03-12 23:58:56 -06:00 |
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tangxifan
|
773e6da308
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Spot a bug in lb router where path finder fail to use low-occupancy node when expanding the tree
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2020-03-12 22:53:17 -06:00 |
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tangxifan
|
f90dc5c296
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remove redundant XML codes
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2020-03-12 20:44:07 -06:00 |
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tangxifan
|
29450f3472
|
debugging multi-source lb router
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2020-03-12 20:42:41 -06:00 |
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tangxifan
|
8921905bec
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annotate multiple-source and multiple-sink nets from pb to lb router
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2020-03-12 19:21:13 -06:00 |
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tangxifan
|
f0b22aaa11
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Make lb router support multiple sources to be routed
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2020-03-12 13:44:14 -06:00 |
|
tangxifan
|
c40675ca9d
|
minor code formatting
|
2020-03-12 11:55:25 -06:00 |
|
tangxifan
|
f1e8e78410
|
minor code formatting
|
2020-03-12 11:47:42 -06:00 |
|
tangxifan
|
689c50dff1
|
label the routing status for each sink in lb_router
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2020-03-12 11:36:31 -06:00 |
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tangxifan
|
a1f19e776e
|
Add comments to lb router and extract a private function for routing a single net
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2020-03-12 11:05:38 -06:00 |
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tangxifan
|
cd50155e29
|
rename variables in lb router
|
2020-03-12 10:24:38 -06:00 |
|
tangxifan
|
17a1c61b9d
|
minor change in variable names in lb_router
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2020-03-11 21:10:16 -06:00 |
|
tangxifan
|
8e796f152f
|
add comments to lb_router about how-to-use
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2020-03-11 21:05:06 -06:00 |
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tangxifan
|
2a260a05aa
|
add a microbenchmark `and_latch` to test LUTs in wired mode
|
2020-03-11 10:40:59 -06:00 |
|
tangxifan
|
1d766d2a70
|
minor format fix on documentation
|
2020-03-11 10:22:30 -06:00 |
|
Xifan Tang
|
b941ac8a4a
|
remove deprecated options
|
2020-03-10 20:58:00 -06:00 |
|
Xifan Tang
|
8037d1ad93
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-03-10 20:55:02 -06:00 |
|
Xifan Tang
|
9f743f7f4e
|
add openfpga shell documentation
|
2020-03-10 20:54:42 -06:00 |
|
tangxifan
|
0da6f00af5
|
start reworking the openfpga tool documentation
|
2020-03-10 17:29:35 -06:00 |
|
tangxifan
|
089cc5e86e
|
update documentation on circuit model annotation on VPR architecture
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2020-03-10 16:51:50 -06:00 |
|
tangxifan
|
7195564455
|
reworked circuit model examples in documentation. Now we are consistent to latest syntax
|
2020-03-10 16:17:20 -06:00 |
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tangxifan
|
8db257946c
|
remove backport in travis setup. The link is dead now. Plus we no longer need the backport for a newer version of cmake
|
2020-03-10 12:18:39 -06:00 |
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tangxifan
|
54dfdc0cc1
|
update general documentation on circuit library
|
2020-03-10 12:18:12 -06:00 |
|
tangxifan
|
2a3c5b98a5
|
minor format fix in documentation
|
2020-03-09 21:25:13 -06:00 |
|
Xifan Tang
|
d14fa16905
|
finish documentation update on technology library
|
2020-03-09 21:17:25 -06:00 |
|
Xifan Tang
|
cb7e4a1dfa
|
finish documentation the simulation settings in VPR8 integration
|
2020-03-09 20:03:37 -06:00 |
|
tangxifan
|
751735bf41
|
update documentation in simulation setting syntax
|
2020-03-09 17:40:33 -06:00 |
|
tangxifan
|
3c7fd30e12
|
merged tutorial to online documentation and reworked compilation guidelines
|
2020-03-09 13:58:24 -06:00 |
|
tangxifan
|
af6319a6b0
|
reworked motivation in documentation
|
2020-03-09 11:27:25 -06:00 |