tangxifan
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b6bdf78d95
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bug fixed for heterogeneous block instances in top module
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2020-03-24 17:39:26 -06:00 |
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tangxifan
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c5049a1ec8
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keep debugging tile direct connections
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2020-03-20 15:10:00 -06:00 |
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tangxifan
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a46fc9f028
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add debugging information for tile direct builder
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2020-03-20 14:59:46 -06:00 |
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tangxifan
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9837be618d
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start debugging tile direct with micro architecture
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2020-03-20 14:52:52 -06:00 |
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tangxifan
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17a1c61b9d
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minor change in variable names in lb_router
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2020-03-11 21:10:16 -06:00 |
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tangxifan
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a6c2d2c7d1
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bug fixed for io location mapping
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2020-02-28 14:46:01 -07:00 |
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tangxifan
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80bb2baae5
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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tangxifan
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542fadaaae
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allow users to use VPR critical path delay in OpenFPGA simulation
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2020-02-28 12:10:27 -07:00 |
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tangxifan
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1b66e837ba
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bug fixing for lb router. Add physical mode to default node expanding settings
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2020-02-21 11:29:00 -07:00 |
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tangxifan
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e842150cc5
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add lut module builder
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2020-02-12 19:52:41 -07:00 |
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tangxifan
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fddd3c9463
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add mux module builder
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2020-02-12 19:45:14 -07:00 |
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tangxifan
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02d6256e95
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pass simple test on pb_type annotation for frac_lut5 architecture
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2020-01-30 21:39:44 -07:00 |
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tangxifan
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1651c9ca18
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add binding between physical pb_type and circuit models
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2020-01-28 16:03:02 -07:00 |
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tangxifan
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01c80b9126
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add sample architecture to be used for Openfpga
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2020-01-27 13:39:13 -07:00 |