3 Commits

Author	SHA1	Message	Date
tangxifan	b010fc1983	add warning to force formal_verification_top_netlist enabled	2020-02-27 13:28:21 -07:00
tangxifan	078f72320f	debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports	2020-02-27 13:24:26 -07:00
tangxifan	f558405887	ported verilog testbench generator online. Split from fabric generator. Testing to be done	2020-02-27 12:33:09 -07:00