riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
2,780 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

2780 Commits

Author SHA1 Message Date
tangxifan 0b1c8ac139 bug fixed in identifying the physical interconnect for pb_graph nodes 2020-04-07 19:46:42 -06:00
tangxifan 62276f9e28 minor code format 2020-04-07 18:43:11 -06:00
tangxifan dd4f83a374 bug fixing to constant string to display interconnect names 2020-04-07 18:28:19 -06:00
tangxifan ff7ea99381 bug fixed in register scan-chain architecture 2020-04-07 17:06:16 -06:00
tangxifan 2342d7cdc6 minor tweak on the scan-chain support in VPR8 as well as architecture file 
Do NOT use pack patterns for the scan-chain. It will cause searching root chain in VPR8 to fail
Actually, we do not use scan-chain in mapping designs. Disable the pack pattern has no impact
 2020-04-07 17:03:44 -06:00
tangxifan 50bb04d496 add scan-chain test case. Debugging on the way 2020-04-07 16:50:41 -06:00
tangxifan cbcd1d20d4 fixed memory leakage in pb_pin fixup 2020-04-07 16:24:04 -06:00
tangxifan 5a04da2082 fix memory leakage in openfpga title 2020-04-07 16:14:41 -06:00
tangxifan 6daee8c2c8 bug fixed in the example architecture 2020-04-07 16:03:34 -06:00
tangxifan 628ea3b654 improve adder chain arch XML to support sequential output for sumout 2020-04-07 15:39:37 -06:00
tangxifan 26d1261c1f add test cases using shift registers 2020-04-07 15:09:10 -06:00
Xifan Tang 307ef58c45 update README to remove dead links 2020-04-07 12:30:23 -06:00
Xifan Tang 55e68896d6 doc update for the support on std cell MUX2 and examples 2020-04-07 12:01:13 -06:00
tangxifan e61e7167b3 update circuit model names in the example tree-like MUX architecture 2020-04-07 11:27:16 -06:00
tangxifan 0eeb8e5317 clean up example architecture XML by removing redundant syntax 2020-04-07 11:24:42 -06:00
tangxifan 6d6295ef93 Add test cases about using standard cell mux2 2020-04-07 11:12:47 -06:00
tangxifan d39d7a68ce add test cases for using tree-like multiplexer 2020-04-07 10:46:49 -06:00
tangxifan 92a3a444f9 update VPR7 to support global I/O ports 2020-04-06 20:44:00 -06:00
Xifan Tang 7a4137fdcf doc update for packable XML syntax in VPR 2020-04-06 18:37:05 -06:00
tangxifan 13cd48c119 add support on packable/unpackable modes in VPR architecture 2020-04-06 16:07:49 -06:00
tangxifan 7e89c2c65f Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2020-04-06 14:10:38 -06:00
tangxifan 6eb125ec2a Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML 2020-04-06 14:09:52 -06:00
ganeshgore 87c25a6084 Added GCC paths to source 2020-04-06 00:35:28 -06:00
ganeshgore e1db4df744 Created task for FPGA shell run 2020-04-06 00:35:07 -06:00
ganeshgore ea4122a8a4 Updated openfpga_flow and task file to support sheel run 2020-04-06 00:34:36 -06:00
ganeshgore 7f98ecc8a6 OpenFPGA shell run test script template 2020-04-06 00:32:43 -06:00
ganeshgore eb3b02277a Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
ganeshgore 77f7e13ba7 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2020-04-05 20:59:10 -06:00
Xifan Tang 1a3a748dd2 update documentation with the support on spypads and global I/O ports 2020-04-05 20:12:28 -06:00
tangxifan 3369d724e9 bug fixing in Verilog top-level testbench generation 2020-04-05 17:50:11 -06:00
tangxifan decc1dc4b2 debugged global gp input/output port support 2020-04-05 17:39:30 -06:00
tangxifan bcb86801fa bug fixed in gpio naming for module manager ports 2020-04-05 17:26:44 -06:00
tangxifan 5f4e7dc5d4 support gpinput and gpoutput ports in module manager and circuit library 2020-04-05 16:52:21 -06:00
tangxifan bc47b3ca94 update verilog module writer to the global spy ports 2020-04-05 16:04:13 -06:00
tangxifan 8b583b7917 debugging spy port builder in module manager 2020-04-05 16:01:25 -06:00
tangxifan ca45efd13d add testing script for the spy io 2020-04-05 15:24:40 -06:00
tangxifan 3b63ad6657 add test openfpga arch XML with spy pad 2020-04-05 15:23:07 -06:00
tangxifan 836f722f20 start supporting global output ports in module manager 2020-04-05 15:19:46 -06:00
ganeshgore d1d3446568 backedup partial upgrade for fpga_flow script 2020-04-05 11:36:24 -06:00
tangxifan 32c74ad811 added FPGA architecture with I/Os on the left and right sides 2020-04-01 15:46:38 -06:00
Xifan Tang 6ce0fe4ef2 doc update for FPGA-bitstream to better motivate the different types of bitstream 2020-04-01 12:57:28 -06:00
Xifan Tang fd8248d9dd update documentation: the addon syntax on VPR and configuration protocols 2020-04-01 12:35:52 -06:00
tangxifan 63306ce3a0 add comments to explain the memory organization in the top-level module 2020-04-01 11:05:30 -06:00
tangxifan 5d12f499f0 hotfix on undriven pins on the connection blocks 2020-03-29 16:26:23 -06:00
tangxifan 07e1979498 add architecture examples on wide memory blocks (width=2). tileable routing is working 2020-03-28 15:41:26 -06:00
tangxifan ff9cc50527 relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads 2020-03-27 20:09:50 -06:00
tangxifan e601a648cc relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics 2020-03-27 19:07:34 -06:00
tangxifan 34a1b61ecb add an example FPGA architecture with AIB interface at the right side of I/Os 2020-03-27 18:45:27 -06:00
tangxifan 4bf0a63ae6 bug fixed for multiple io types defined in FPGA architectures 2020-03-27 16:32:15 -06:00
tangxifan 7c9c2451f2 debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric 2020-03-27 16:03:42 -06:00