tangxifan
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e6c896d583
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now inout must be global port and I/O port so that it will appear in the top-level module
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2020-04-08 16:54:08 -06:00 |
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tangxifan
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50bb04d496
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add scan-chain test case. Debugging on the way
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2020-04-07 16:50:41 -06:00 |
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tangxifan
|
26d1261c1f
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add test cases using shift registers
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2020-04-07 15:09:10 -06:00 |
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tangxifan
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e61e7167b3
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update circuit model names in the example tree-like MUX architecture
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2020-04-07 11:27:16 -06:00 |
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tangxifan
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0eeb8e5317
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clean up example architecture XML by removing redundant syntax
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2020-04-07 11:24:42 -06:00 |
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tangxifan
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6d6295ef93
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Add test cases about using standard cell mux2
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2020-04-07 11:12:47 -06:00 |
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tangxifan
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d39d7a68ce
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add test cases for using tree-like multiplexer
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2020-04-07 10:46:49 -06:00 |
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tangxifan
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6eb125ec2a
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Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
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2020-04-06 14:09:52 -06:00 |
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tangxifan
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bcb86801fa
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bug fixed in gpio naming for module manager ports
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2020-04-05 17:26:44 -06:00 |
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tangxifan
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5f4e7dc5d4
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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tangxifan
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3b63ad6657
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add test openfpga arch XML with spy pad
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2020-04-05 15:23:07 -06:00 |
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tangxifan
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ff9cc50527
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relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
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2020-03-27 20:09:50 -06:00 |
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tangxifan
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e601a648cc
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relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
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2020-03-27 19:07:34 -06:00 |
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tangxifan
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b6bdf78d95
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bug fixed for heterogeneous block instances in top module
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2020-03-24 17:39:26 -06:00 |
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tangxifan
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c5049a1ec8
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keep debugging tile direct connections
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2020-03-20 15:10:00 -06:00 |
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tangxifan
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a46fc9f028
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add debugging information for tile direct builder
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2020-03-20 14:59:46 -06:00 |
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tangxifan
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9837be618d
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start debugging tile direct with micro architecture
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2020-03-20 14:52:52 -06:00 |
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tangxifan
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17a1c61b9d
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minor change in variable names in lb_router
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2020-03-11 21:10:16 -06:00 |
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tangxifan
|
a6c2d2c7d1
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bug fixed for io location mapping
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2020-02-28 14:46:01 -07:00 |
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tangxifan
|
80bb2baae5
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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tangxifan
|
542fadaaae
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allow users to use VPR critical path delay in OpenFPGA simulation
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2020-02-28 12:10:27 -07:00 |
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tangxifan
|
1b66e837ba
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bug fixing for lb router. Add physical mode to default node expanding settings
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2020-02-21 11:29:00 -07:00 |
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tangxifan
|
e842150cc5
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add lut module builder
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2020-02-12 19:52:41 -07:00 |
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tangxifan
|
fddd3c9463
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add mux module builder
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2020-02-12 19:45:14 -07:00 |
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tangxifan
|
02d6256e95
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pass simple test on pb_type annotation for frac_lut5 architecture
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2020-01-30 21:39:44 -07:00 |
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tangxifan
|
1651c9ca18
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add binding between physical pb_type and circuit models
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2020-01-28 16:03:02 -07:00 |
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tangxifan
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01c80b9126
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add sample architecture to be used for Openfpga
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2020-01-27 13:39:13 -07:00 |