tangxifan
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da157ed5de
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[test] debugging git-diff
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2022-09-20 15:31:39 -07:00 |
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tangxifan
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3f8106f12e
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[arch] fixed a bug in the custom I/O location assignment: no more I/Os on the corner of centre fabric
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2022-09-20 15:19:32 -07:00 |
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tangxifan
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b630d60b7e
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[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
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2022-09-20 14:14:18 -07:00 |
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tangxifan
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6a896a9845
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[test] debugging
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2022-09-20 14:08:22 -07:00 |
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tangxifan
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ecfdc4a83a
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[test] debugging
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2022-09-20 13:51:32 -07:00 |
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tangxifan
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abee802830
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[script] now build task_result.csv from openfpgashell.log rather than vpr_stdout.log because of missing block usage numbers
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2022-09-20 13:46:30 -07:00 |
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tangxifan
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bdcdc7d294
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[test] Now git diff in basic regression tests should capture the changes on golden outputs
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2022-09-20 13:36:31 -07:00 |
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tangxifan
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37c5056d6a
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[test] now use a fixed routing channel width for quicklogic tests
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2022-09-20 12:25:40 -07:00 |
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tangxifan
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846ca26311
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[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
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2022-09-20 12:08:24 -07:00 |
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tangxifan
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b3449a338f
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[arch] update out-of-date vpr arch from v1.1 to v1.2
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2022-09-20 09:51:43 -07:00 |
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tangxifan
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63cb8d589d
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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tangxifan
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40663f956c
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[test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability
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2022-09-19 21:55:15 -07:00 |
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tangxifan
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d9bd0a6cf3
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[test] disable clustering-routing result sync-up when calling vpr in example scripts
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2022-09-19 20:52:04 -07:00 |
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tangxifan
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fca1c82388
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[test] disable clustering and routing sync when using VPR
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2022-09-19 20:33:35 -07:00 |
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tangxifan
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e19ca1c6d1
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[engine] fixed a bug when decoding bitstream for connnection blocks: now use incoming edges from gsb
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2022-09-19 18:49:54 -07:00 |
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tangxifan
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1177e8740e
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[engine] update vtr
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2022-09-19 15:35:23 -07:00 |
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tangxifan
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9b0a97d391
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[engine] update vtr
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2022-09-19 15:05:45 -07:00 |
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tangxifan
|
c922259c23
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[engine] remove warnings and update vtr
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2022-09-19 14:53:30 -07:00 |
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tangxifan
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90ddd2ce32
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[engine] now get incoming edges for IPINs only from GSB
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2022-09-19 14:02:13 -07:00 |
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tangxifan
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5eba2d7f6f
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[engine] update vpr
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2022-09-19 13:31:08 -07:00 |
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tangxifan
|
050b6edcba
|
[engine] update vtr
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2022-09-19 13:23:14 -07:00 |
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tangxifan
|
3c6ef1925c
|
[engine] now sort ipin incoming edges
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2022-09-19 11:00:08 -07:00 |
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tangxifan
|
87c63d1437
|
[engine] update vtr
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2022-09-19 10:20:19 -07:00 |
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tangxifan
|
c340330ae0
|
[engine] update vtr
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2022-09-19 09:54:57 -07:00 |
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tangxifan
|
a7416d285f
|
[engine] update vpr
|
2022-09-18 22:14:12 -07:00 |
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tangxifan
|
fec6905c20
|
[engine] update vtr
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2022-09-18 21:57:22 -07:00 |
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tangxifan
|
7cfc50aa8f
|
[vtr] update engin
|
2022-09-18 21:46:06 -07:00 |
|
tangxifan
|
d1334ef8c9
|
[engine] update vtr
|
2022-09-18 10:58:37 -07:00 |
|
tangxifan
|
76720dfe16
|
[engine] update vtr
|
2022-09-18 10:05:30 -07:00 |
|
tangxifan
|
370ddcc1ed
|
[engine] update vtr
|
2022-09-17 22:24:07 -07:00 |
|
tangxifan
|
fa2cc87d0a
|
[engine] update vtr
|
2022-09-17 10:25:33 -07:00 |
|
tangxifan
|
4dd90f4466
|
[engine] update vtr
|
2022-09-17 10:22:41 -07:00 |
|
tangxifan
|
29fff9e139
|
[engine] update vtr
|
2022-09-17 09:57:25 -07:00 |
|
tangxifan
|
fcf4525870
|
[engine] update vtr
|
2022-09-17 09:52:33 -07:00 |
|
tangxifan
|
9e8c6be408
|
[engine] update vtr
|
2022-09-16 21:42:48 -07:00 |
|
tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
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tangxifan
|
e98d022d3a
|
[engine] update vtr
|
2022-09-16 16:23:14 -07:00 |
|
tangxifan
|
30988d7072
|
Merge pull request #794 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-09-16 13:59:48 -07:00 |
github-actions[bot]
|
d3019c1642
|
Updated Patch Count
|
2022-09-16 20:28:38 +00:00 |
|
tangxifan
|
b7b82804ff
|
Merge pull request #792 from lnis-uofu/io_indexing
Now I/O indexing follows a natural way (clockwise) throughout the fabric.
|
2022-09-16 12:01:25 -07:00 |
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tangxifan
|
a8d7b6c2c4
|
[script] add a python script for users to visualize the I/O sequence
|
2022-09-16 10:49:10 -07:00 |
|
tangxifan
|
f0fe781dbc
|
[engine] fixed a bug
|
2022-09-16 10:45:27 -07:00 |
|
tangxifan
|
a2e22787c2
|
[test] deploy the new test cases to the basic regression tests
|
2022-09-16 10:31:15 -07:00 |
|
tangxifan
|
10e86d334a
|
[test] add test cases to validate the various layouts where I/Os are in the center of the grid
|
2022-09-16 10:29:19 -07:00 |
|
tangxifan
|
f2e13e5ea9
|
[arch] add more flexible layout to test I/O center features
|
2022-09-16 10:00:08 -07:00 |
|
tangxifan
|
bba5b7b070
|
[engine] syntax
|
2022-09-15 23:04:37 -07:00 |
|
tangxifan
|
cbc71c75c4
|
[engine] now io indexing follows a natural way
|
2022-09-15 23:01:35 -07:00 |
|
tangxifan
|
b0b3d52e66
|
Merge pull request #787 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2022-09-14 19:42:01 -07:00 |
|
github-actions[bot]
|
7903bb40f0
|
Updated Patch Count
|
2022-09-15 02:39:51 +00:00 |
|
tangxifan
|
7016c9e4c8
|
Merge pull request #785 from lnis-uofu/io_center
Support I/Os in the center of the FPGA fabric
|
2022-09-14 18:34:28 -07:00 |