4 Commits

Author	SHA1	Message	Date
tangxifan	0ec465d4e1	refactoring auto-check top Verilog testbench	2019-11-03 17:41:29 -07:00
tangxifan	dc241e6c03	add explicit port mapping support in testbenches; remove dangling ports in benchmarks	2019-11-02 23:03:47 -06:00
tangxifan	531cc064fc	bug fixing for formal top-level testbench	2019-11-01 10:47:40 -06:00
tangxifan	a6a3e7c36b	adding mcnc_big20 to regression test	2019-10-31 19:31:27 -06:00