tangxifan
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ee59bdb675
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[core] code format
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2023-06-07 18:55:34 -07:00 |
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tangxifan
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327f7f4dab
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[core] now adapt to latest API of DeviceGrid
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2023-06-07 18:54:48 -07:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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ce32c3b30b
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[engine] fixing api errors
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2022-08-17 14:47:14 -07:00 |
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tangxifan
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3c2bf5159b
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[engine] use new API to get node side
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2022-08-17 14:38:40 -07:00 |
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tangxifan
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0c329866da
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[engine] Use RRGraphView in openfpga source codes
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2022-08-16 16:48:32 -07:00 |
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tangxifan
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c8d41b4e69
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[Tool] Change routing module port naming to include architecture port names
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2021-03-14 19:35:49 -06:00 |
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tangxifan
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0a3c746fb1
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now split CB module bus ports into lower/upper parts
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2020-07-01 14:37:13 -06:00 |
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tangxifan
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05187f8aa4
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use typedef to short the module pin information
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2020-06-30 18:07:22 -06:00 |
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tangxifan
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2e7684b746
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adapt bus ports in connection block module builder
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2020-06-30 17:50:53 -06:00 |
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tangxifan
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2ef083c49d
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adapt SB module builder to use bus ports
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2020-06-30 16:02:40 -06:00 |
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tangxifan
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cf440f92d3
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put routing module builder util function online
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2020-02-13 16:05:23 -07:00 |