tangxifan
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d9d57aad42
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[Tool] Added default net type options to verilog testbench generator command
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2021-06-14 11:37:49 -06:00 |
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tangxifan
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0670c2de59
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[Tool] Deploy pin constraints to preconfig Verilog module generation
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2021-01-19 16:56:30 -07:00 |
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tangxifan
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dcb50e4f19
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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tangxifan
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ba0120bd76
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[Tool] Remove the limitation on requiring Qb ports for CCFF
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2020-11-06 11:10:04 -07:00 |
ganeshgore
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559564c333
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-06-12 17:31:14 -06:00 |
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tangxifan
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bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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8f5a684b10
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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tangxifan
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185e574738
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removed redundant include files in all the verilog netlists except the top one
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2020-04-24 20:21:32 -06:00 |
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tangxifan
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9b769cd8e4
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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tangxifan
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f558405887
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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tangxifan
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e9adb4fdbc
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add preconfig top module Verilog generation
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2020-02-26 20:38:01 -07:00 |