Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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0d14aa4cb8
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[Flow] Add comments to clarify the limitations
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2021-10-30 19:17:11 -07:00 |
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tangxifan
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6277234125
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[Flow] bug fix in BRAM-oriented yosys scripts
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2021-10-30 15:34:30 -07:00 |
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tangxifan
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0b770f3330
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[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
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2021-10-30 14:36:43 -07:00 |
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tangxifan
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9c06041ce4
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[Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff`
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2021-10-30 11:27:40 -07:00 |
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tangxifan
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dd46780865
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[Script] Update yosys script using BRAMs
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2021-04-27 21:44:27 -06:00 |
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tangxifan
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7eeb35d21f
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[Script] Bug fix in yosys script to synthesis BRAM
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2021-03-17 15:12:04 -06:00 |
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tangxifan
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094b3e9b90
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[Script] Use parameters in template yosys script supporting BRAMs
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2021-03-16 19:51:48 -06:00 |
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tangxifan
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84778bd38d
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[Script] Add new yosys script to support architectures with BRAMs
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2021-03-16 16:52:18 -06:00 |