4 Commits

Author	SHA1	Message	Date
tangxifan	3cf7950bc1	add wire module generation and simplify Verilog generation for wires	2019-10-21 20:20:34 -06:00
tangxifan	b920f0fc38	refactored user template Verilog generation	2019-09-13 11:41:54 -06:00
tangxifan	c20e182484	plugged in the refactored wire Verilog generation	2019-09-12 20:56:30 -06:00
tangxifan	2b829238b5	refactored wire Verilog generation	2019-09-12 20:49:02 -06:00