5 Commits

Author	SHA1	Message	Date
tangxifan	9cf8683acd	add module generation for memories	2019-10-22 15:31:08 -06:00
tangxifan	56f40cf46c	light modification on Verilog Mux generation and start refactoring memory Verilog generation	2019-09-13 12:22:57 -06:00
tangxifan	2b829238b5	refactored wire Verilog generation	2019-09-12 20:49:02 -06:00
tangxifan	8fc258cc93	develop and plug mux_lib_builder, refactoring the mux submodule generation	2019-08-25 15:33:37 -06:00
tangxifan	19472ace4e	renaming files	2019-08-20 21:01:38 -06:00