4 Commits

Author	SHA1	Message	Date
tangxifan	7c116aac2f	added Verilog generation for preconfig top module	2019-10-29 13:54:35 -06:00
tangxifan	520e145af2	move mux_lib to fpga_x2p_setup	2019-10-19 19:13:52 -06:00
tangxifan	04f0fbebf7	plug in module graph to feed verilog writers	2019-10-18 21:59:22 -06:00
tangxifan	46d44fa42a	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00