Xifan Tang
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42da9160f0
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Clean codes and update
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2018-09-04 17:49:20 -06:00 |
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Xifan Tang
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9f3cb45b85
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
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2018-09-04 17:33:38 -06:00 |
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Xifan Tang
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00ecd0bb1d
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Cleanup codes and organization
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2018-09-04 17:31:30 -06:00 |
tangxifan
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d3d95ee842
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Update getting_started.md
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2018-08-10 14:17:12 -06:00 |
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Xifan Tang
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cb15bb5082
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Clean code and fix minor bugs
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2018-08-10 13:46:00 -06:00 |
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Xifan Tang
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b0ef554b35
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Add power property XML
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2018-08-09 11:27:36 -06:00 |
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Xifan Tang
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90669d19c5
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Update FPGA-SPICE and flow configurations
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2018-08-09 11:27:16 -06:00 |
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Xifan Tang
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4d7f4350de
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get FPGA-SPICE updated for release - Clear printf and fix assert bugs
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2018-08-01 14:04:28 -06:00 |
Steve Corey
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91f073cdc4
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added build files to .gitignore
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2018-07-30 10:36:34 -06:00 |
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Xifan Tang
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fe13168f8f
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Add ABC and ACE2, fix bugs for fpga_flow and VPR
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2018-07-27 22:54:52 -06:00 |
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Steve Corey
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b9d583519b
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
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2018-07-26 13:59:26 -06:00 |
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Steve Corey
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be6c296c22
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initial commit of black-box doc
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2018-07-26 13:58:58 -06:00 |
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Xifan Tang
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158dec405e
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Reorganize the code directory
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2018-07-26 11:28:21 -06:00 |
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Steve Corey
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3abce69f7c
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multimode clb simple documentation complete
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2018-07-18 10:54:05 -06:00 |
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Steve Corey
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c61d11baa6
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changed some names to make more sense
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2018-07-18 10:53:21 -06:00 |
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Steve Corey
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9c4e5ca95f
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ignored vpr output files
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2018-07-18 10:50:37 -06:00 |
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Steve Corey
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1b36d491c8
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ignored vpr output files
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2018-07-18 10:48:55 -06:00 |
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Steve Corey
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51efa38751
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continuing simple documentation
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2018-07-17 13:55:10 -06:00 |
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Steve Corey
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84fd0348af
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initial commit of simple architecture documentation
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2018-07-16 13:22:18 -06:00 |
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Steve Corey
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6f73b7a874
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moved architecture documentation to new file
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2018-07-16 13:21:41 -06:00 |
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Steve Corey
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17988e2ade
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changed switch names to make more sense
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2018-07-16 13:21:07 -06:00 |
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Steve Corey
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fa50eef093
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added simple architecture for vpr version 8
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2018-07-11 13:19:40 -06:00 |
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Steve Corey
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2208916a95
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updated to line numbers of vpr8 example architecture
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2018-07-10 13:02:21 -06:00 |
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Steve Corey
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8040328841
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added notes about CLB
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2018-07-09 13:06:22 -06:00 |
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Steve Corey
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8c7a7af458
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started documenting architecture
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2018-07-06 13:36:55 -06:00 |
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Steve Corey
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5b6ce1349e
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edited to match vtr_release7 version
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2018-07-05 11:54:37 -06:00 |
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Steve Corey
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3f00ce365e
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tutorial additions
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2018-07-03 15:04:09 -06:00 |
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Steve Corey
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2cc4027ab0
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added tutorial files
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2018-07-03 14:46:50 -06:00 |
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Steve Corey
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122c1b19f7
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removed cloning
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2018-07-02 11:12:28 -06:00 |
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stevecorey
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569bdbfb95
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added submodule instructions
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2018-06-29 13:30:44 -06:00 |
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stevecorey
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cfcc177e4b
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added submodule instructions
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2018-06-29 13:29:56 -06:00 |
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stevecorey
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d5c0c7659b
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removed cloning
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2018-06-29 13:24:18 -06:00 |
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stevecorey
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f8e1e06a6c
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added git cloning and tool building
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2018-06-29 11:16:13 -06:00 |
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stevecorey
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6f4b7f5cb9
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added tangxifan-eda-tools as a submodule
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2018-06-28 12:59:12 -06:00 |
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stevecorey
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099e180557
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initial commit
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2018-06-28 12:47:59 -06:00 |
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stevecorey
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8c341d8f51
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initial commit
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2018-06-28 11:50:25 -06:00 |
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stevecorey
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7b1e82e9c8
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
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2018-06-27 11:54:17 -06:00 |
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stevecorey
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6430fc5139
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initial commit
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2018-06-27 11:54:00 -06:00 |
Pierre-Emmanuel Gaillardon
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508346c196
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Create LICENSE
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2018-06-26 21:52:08 -07:00 |
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LNIS-Projects
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520e9ae64b
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initial commit
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2018-06-26 17:41:36 -06:00 |