5 Commits

Author	SHA1	Message	Date
tangxifan	fd99dafad7	[core] code format	2023-09-25 16:51:01 -07:00
tangxifan	ca715f4c82	[core] developing parser to support subtile port merge	2023-09-25 16:46:34 -07:00
tangxifan	60ff298987	[lib] add new feature to enable clock tree connection to global ports of tiles	2023-02-28 22:36:41 -08:00
tangxifan	6d31b319a2	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
tangxifan	e909f4fabe	[lib] rename libopenfpga to libs	2022-08-18 10:27:20 -07:00