3 Commits

Author	SHA1	Message	Date
tangxifan	9a906e787b	[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock	2021-01-13 15:43:31 -07:00
tangxifan	7af6d7f07d	[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation	2021-01-13 15:38:44 -07:00
tangxifan	ccf3e037ff	[Benchmark] Change multi-clock counter from 8-bit to 4-bit	2021-01-13 13:31:06 -07:00