Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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ff264c00a2
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
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2021-10-31 11:51:34 -07:00 |
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tangxifan
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c8e9dfbeda
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[Test] bug fix
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2021-10-30 16:50:57 -07:00 |
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tangxifan
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335347a74f
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[Test] Bug fix
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2021-10-30 15:48:25 -07:00 |
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tangxifan
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be47e78289
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[Arch] Change arch for Sapone test
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2021-10-30 15:23:19 -07:00 |
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tangxifan
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ad5cce0ae8
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[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
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2021-10-30 15:11:07 -07:00 |
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tangxifan
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16de60e943
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[Test] Turn off ACE2 run in bitstream generation only flows
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2021-10-30 12:31:14 -07:00 |
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tangxifan
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189ade6c1e
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[Test] Bug fix
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2021-10-05 19:17:34 -07:00 |
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tangxifan
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f74ea5d39a
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[Test] Use the new openfpga shell script in don't care bit tests
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2021-10-05 19:14:44 -07:00 |
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tangxifan
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50604e4589
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[Test] move test cases
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2021-10-05 19:02:43 -07:00 |
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tangxifan
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fed6c133b1
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[Test] Add new tests to validate the correctness of bitstream files with don't care bits
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2021-10-05 18:59:33 -07:00 |
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tangxifan
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2baf3ddd2f
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[Test] Add test cases for 'report_bitstream_distribution' command
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2021-05-07 12:06:24 -06:00 |
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tangxifan
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b8ced5377f
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[Test] Add a test case for i/o mapping writer
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2021-04-27 14:41:15 -06:00 |
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tangxifan
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578d81b67a
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[Test] Patch task configuration file
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2021-04-19 16:15:00 -06:00 |
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tangxifan
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5976cc0a1c
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[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
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2021-04-19 15:54:18 -06:00 |
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tangxifan
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e19fc15fec
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[Test] bug fix in test case
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2021-02-18 19:37:45 -07:00 |
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tangxifan
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2e88b035ed
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[Test] Add wire LUT repacker test case
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2021-02-18 19:37:44 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
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efad0402c2
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[Regression Test] Bug fix for CI errors
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2020-09-24 13:55:41 -06:00 |
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tangxifan
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e4291eb27e
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[Regression Tests] Now use fixed device layout in test cases for best coverage
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2020-09-21 18:44:13 -06:00 |
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tangxifan
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f33422d4d7
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add regression test to track runtime on big fpga devices using practical benchmarks
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2020-07-28 12:38:42 -06:00 |
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tangxifan
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5d83abb2cf
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bug fix in read architecture bitstream and regression tests
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2020-07-27 19:37:05 -06:00 |
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tangxifan
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5595ee9052
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refine the test case for load external arch bitstream
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2020-07-27 16:53:29 -06:00 |
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tangxifan
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cec6bf0b6f
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add or2 microbenchmark for testing external arch bitstream
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2020-07-27 15:59:03 -06:00 |
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tangxifan
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4174fbf77d
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add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
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2020-07-27 15:54:46 -06:00 |