tangxifan
|
372fb261fd
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[Tool] Extend the support on global tile port for I/O tiles
|
2020-11-11 15:09:40 -07:00 |
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tangxifan
|
bc43c876b0
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[Doc] Update documentation for the rules in global port definition for tile ports
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2020-11-11 14:10:11 -07:00 |
|
tangxifan
|
e959821813
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[Tool] Enhance internal check functions for tile annotation
|
2020-11-11 13:59:24 -07:00 |
|
tangxifan
|
e627b6dd5d
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[Tool] Enhance port attribute checks in tile annotation data structure
|
2020-11-11 13:41:05 -07:00 |
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tangxifan
|
9cbc374b33
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[Tool] Add check codes for tile annotation
|
2020-11-11 12:03:13 -07:00 |
|
tangxifan
|
81e56d45d6
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[Tool] Update FPGA-SDC to use the new data structure for global ports
|
2020-11-10 21:17:17 -07:00 |
|
tangxifan
|
2c269c532a
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[Doc] Update doc for the global port definition using physical tile port
|
2020-11-10 20:48:28 -07:00 |
|
tangxifan
|
4dc0fb81c5
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[Tool] Bug fix for clang compilation error
|
2020-11-10 20:32:58 -07:00 |
|
tangxifan
|
c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
|
2020-11-10 20:31:14 -07:00 |
|
tangxifan
|
05f5ce38ea
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[Test] Deploy new test to CI
|
2020-11-10 20:31:03 -07:00 |
|
tangxifan
|
485258a9ea
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[Test] Add test case for global clock from tiles
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2020-11-10 19:24:25 -07:00 |
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tangxifan
|
f29916921a
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[Arch] Add openfpga arch for using global clocks from tiles
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2020-11-10 19:20:08 -07:00 |
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tangxifan
|
a6531d9e8d
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[Arch] Add k4 arch using global clock from tile port (with zero fc)
|
2020-11-10 19:17:34 -07:00 |
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tangxifan
|
dcb50e4f19
|
[Tool] Use use standard data structure to store global port information
|
2020-11-10 19:07:28 -07:00 |
|
tangxifan
|
cbb1545ee3
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[Tool] Add connection builder for tile global ports to top-level module
|
2020-11-10 16:59:00 -07:00 |
|
tangxifan
|
67af145455
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[Tool] Add XML writer for tile annotation
|
2020-11-10 14:51:46 -07:00 |
|
tangxifan
|
75ce4b5e25
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[Arch] Fine tune example arch
|
2020-11-10 14:38:47 -07:00 |
|
tangxifan
|
6fbdbe68ae
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[Tool] Add tile annotation parser
|
2020-11-10 14:32:24 -07:00 |
|
tangxifan
|
d127304760
|
[Arch] Update sample arch using local clock from physical tile ports
|
2020-11-10 14:31:58 -07:00 |
|
tangxifan
|
4ca2a129c2
|
[Arch] Add an sample architecture where global clock port is defined from tile ports
|
2020-11-10 11:47:03 -07:00 |
|
tangxifan
|
5fe9c27600
|
[Tool] Remove redundant assertation
|
2020-11-09 09:42:39 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
520e54d7ab
|
Merge pull request #118 from LNIS-Projects/dev
Remove the restrictions on requiring two outputs for configurable memory circuits
|
2020-11-06 13:25:29 -07:00 |
|
tangxifan
|
056b7c0c79
|
[Doc] Update documentation about CCFF circuit model examples
|
2020-11-06 12:22:22 -07:00 |
|
tangxifan
|
70734abc35
|
[Arch] Remove QN from stdcell arch
|
2020-11-06 11:20:13 -07:00 |
|
tangxifan
|
1a79a55646
|
[HDL] Add DFF cell with reset but only 1 output
|
2020-11-06 11:19:19 -07:00 |
|
tangxifan
|
0a273ffab6
|
[Tool] Bug fix in the tight requirements on CCFF circuit model
|
2020-11-06 11:16:46 -07:00 |
|
tangxifan
|
ba0120bd76
|
[Tool] Remove the limitation on requiring Qb ports for CCFF
|
2020-11-06 11:10:04 -07:00 |
|
tangxifan
|
2aab8bf910
|
[Arch] Use single-output DFF for a standard cell FPGA
|
2020-11-06 10:26:39 -07:00 |
|
tangxifan
|
7d46b35296
|
[HDL] Add single-output DFF HDL
|
2020-11-06 10:18:37 -07:00 |
|
tangxifan
|
55b14fa6b4
|
Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-11-06 10:11:38 -07:00 |
|
tangxifan
|
4a53640cf8
|
Merge pull request #117 from olofk/patch-1
Update README.md
|
2020-11-06 09:21:18 -07:00 |
Olof Kindgren
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468c3ff353
|
Update README.md
|
2020-11-06 09:53:11 +01:00 |
|
tangxifan
|
849ecc7fc0
|
[Doc] Add notes for using the is_data_io syntax
|
2020-11-05 09:30:19 -07:00 |
|
tangxifan
|
9bce2f3818
|
[Doc] Update documentation for new XML syntax "is_data_io"
|
2020-11-05 09:28:46 -07:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
55f7a2c187
|
Merge pull request #116 from LNIS-Projects/dev
Extended I/O Support for SoC I/O interface
|
2020-11-04 21:55:37 -07:00 |
|
tangxifan
|
93e7107d80
|
[Test] Add new test to CI
|
2020-11-04 20:59:34 -07:00 |
|
tangxifan
|
bce8233019
|
[Arch] Bug fix in caravel arch
|
2020-11-04 20:58:58 -07:00 |
|
tangxifan
|
6b48ee7f0b
|
[Test] Add new test for caravel io support
|
2020-11-04 20:58:40 -07:00 |
|
tangxifan
|
c85edb4738
|
[Arch] Bug fix for embedded io arch
|
2020-11-04 20:52:47 -07:00 |
|
tangxifan
|
9b0617ffe6
|
[Tool] Bug fix for mappable I/O support
|
2020-11-04 20:45:51 -07:00 |
|
tangxifan
|
a6c7bb2c48
|
[Arch] Update OpenFPGA arch for new syntax on I/O
|
2020-11-04 20:24:02 -07:00 |
|
tangxifan
|
37c10f0cb5
|
[Tool] Add mappable I/O support and enhance I/O support
|
2020-11-04 20:21:49 -07:00 |
|
tangxifan
|
dd86f7f464
|
[Arch] Path architecture for caravel i/o interface
|
2020-11-04 17:16:21 -07:00 |
|
tangxifan
|
c074e88dcd
|
[HDL] Add embedded I/O HDL for Caravel SoC interface
|
2020-11-04 17:09:59 -07:00 |
|
tangxifan
|
aebf7453d0
|
[Arch] Add architecture files with compatible I/O capacity with caravel SoC
|
2020-11-04 16:57:00 -07:00 |
|
tangxifan
|
19f2bf9b38
|
[Test] deploy new test cases to CI
|
2020-11-04 16:35:51 -07:00 |
|
tangxifan
|
61376a2979
|
[Test] Add test cases for various tile organization
|
2020-11-04 16:32:52 -07:00 |
|
tangxifan
|
cf455df555
|
[Arch] Add architecture for bottom-right and top-left tile organization
|
2020-11-04 16:24:36 -07:00 |
|
tangxifan
|
46ca406f10
|
[Arch] Add a new vpr architecture with new tile organization
|
2020-11-04 16:20:01 -07:00 |
|
tangxifan
|
049ca14461
|
[Doc] Add new naming rules for vpr architecture files
|
2020-11-04 16:17:56 -07:00 |