tangxifan
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671188dfa4
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[FPGA-Verilog] Now support big/little-endian in bus group
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2022-02-18 23:05:03 -08:00 |
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tangxifan
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94fea84a40
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[Lib] Fix a bug in memory allocation
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2022-02-18 12:36:03 -08:00 |
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tangxifan
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0d620888ab
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[FPGA-Verilog] Now instance can output bus ports with all the pins
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2022-02-18 12:03:26 -08:00 |
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tangxifan
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c96f0d199d
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[FPGA-Verilog] Adding bus group support in Verilog testbenches
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2022-02-17 23:14:28 -08:00 |
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tangxifan
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e60d7d12b7
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[Lib] Fixed a bug in writer
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2022-02-17 17:12:07 -08:00 |
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tangxifan
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4b3f906f11
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[Lib] Fixed all the syntax errors
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2022-02-17 17:09:03 -08:00 |
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tangxifan
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27627bf5b4
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[Lib] Add an example XML for bus group unit tests
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2022-02-17 16:22:01 -08:00 |
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tangxifan
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0d7e949166
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[Lib] Add unit test for bus group
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2022-02-17 16:21:12 -08:00 |
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tangxifan
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76cf4e1662
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[Lib] Add reader and writer for bus group
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2022-02-17 16:17:37 -08:00 |
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tangxifan
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1edaa04715
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[Lib] Adding XML parser for the bus group
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2022-02-17 15:50:44 -08:00 |
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tangxifan
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b44701bc2c
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[Lib] Adding the 1st version of bus group data structure
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2022-02-17 15:02:37 -08:00 |