0f56dbcb92
[ci] debug
2022-05-09 17:58:17 +08:00
52b348c6db
[ci] debug
2022-05-09 17:54:08 +08:00
15617392ae
[ci] debugging
2022-05-09 17:51:02 +08:00
925ac9051c
[ci] typo
2022-05-09 17:45:31 +08:00
effa9e0f41
[ci] fixed a bug
2022-05-09 17:03:33 +08:00
790628b22e
[ci] add opoenfpga cell library test to ci
2022-05-09 16:08:31 +08:00
8ab090651a
[FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports
2022-03-16 20:51:37 +08:00
8ff68315ab
[CI] Update patch updater due to release v1.1.0
2022-02-20 23:32:11 -08:00
ad7d29b975
build.yml flow is updated with basic_reg_yosys_only_test
2022-01-14 15:45:22 +05:00
3e7169b5e2
corrected syntax error in YAML file
2021-12-21 12:57:57 +05:00
f85cf322bc
remove the pull request trigger
2021-12-20 14:47:34 +05:00
57d977f329
remove the temporary branch name
2021-12-20 14:12:59 +05:00
56b5f1d063
added branch name temporary
2021-12-20 14:09:42 +05:00
e9a4e9ad8d
Corrected typo
2021-12-20 12:54:12 +05:00
89b9487bf8
Trigger on PR to check
2021-12-20 12:52:18 +05:00
0a61c62756
Update and rename patch_updator.yml to patch_updater.yml
2021-12-20 12:40:12 +05:00
7b2cc61d99
added the workflow files to automattically update the patch count
2021-12-20 12:35:02 +05:00
0e86a26ebb
Now CI tests will cancel previous runs
2021-12-10 10:52:01 -08:00
05a0696ced
Reverted debug changes
2021-12-01 14:34:18 -07:00
a60eea2a44
Testing yosys file copy option
2021-12-01 14:01:36 -07:00
192eb1e655
correct yosys paths for CI
2021-11-04 09:11:57 +05:30
f0d81f7ffc
[Bugfix] docker CI build
2021-10-20 14:50:17 -06:00
de53943208
Removed dummy changes
2021-10-18 21:43:05 -06:00
ba7a676429
Updated docker yml
2021-10-18 21:42:39 -06:00
ed5942ce56
Added DOCKER_REPO variable
2021-10-18 20:00:21 -06:00
32f234f4fc
Made LNIS Repo as default
2021-10-18 12:54:31 -06:00
fdc9e318fd
[CI] Addding conditional docker push
2021-10-18 12:18:35 -06:00
d37ae8a8c5
Changed docker repo to github repository
2021-10-18 11:34:59 -06:00
f60f5b4ae5
add wget to list of dependencies
2021-10-08 03:22:30 +05:30
260b14c3d4
[CI] Add the micro benchmark regression test to CI
2021-06-21 18:37:42 -06:00
f395ed2718
[Test] Deploy iwls tests to CI
2021-04-16 16:13:46 -06:00
d22d935322
[CI] Update regressiont tests run in CI script
2021-03-17 16:08:33 -06:00
7a986defba
[CI] Deploy vtr benchmark regression test to CI
2021-03-17 15:15:54 -06:00
66745a85f2
Fixed an issue with the CI workflow
...
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-03-15 09:29:37 +01:00
4eef4bd3d1
[CI/CD] Skipped container login if branch is not master
2021-03-01 17:47:02 -07:00
808df8a87e
[Bugfix] Docker regression using master regression scripts
2021-02-17 13:23:45 -07:00
9c19e2b365
[Test] Move regression test scripts from workflow to openfpga_flow
2021-02-16 11:55:47 -07:00
62bf0d0c5d
[Test] Move quicklogic regresssion tests to a dedicated CI run
2021-02-16 11:00:31 -07:00
9b86f3bb85
Merge branch 'master' into dev
2021-02-09 22:40:45 -07:00
be24c904af
[Test] Add superLUT test case to CI
2021-02-09 21:15:21 -07:00
7b8fd55916
[Bugfix] Task name in regression flow
2021-02-08 12:06:36 -07:00
9c5e1b1478
[CI] Updated test
2021-02-08 11:11:00 -07:00
18070954d8
[CI] Moved test to basic test
2021-02-08 10:20:57 -07:00
ede5f8ed58
[Flow] Support multi-user enviroment for running task
2021-02-07 22:11:04 -07:00
a80acfb547
[Test] Add new test case to CI script
2021-02-01 11:16:12 -07:00
186a0cadfb
Checking complete flow of build.yml from non master branch ( #207 )
...
* [CICD] SHA extraction bug fix
* [CICD] Docker image builds but push from master
* [CICD] General cleanup
2021-01-30 09:40:53 -07:00
52dc76c25e
[CICD] Added SHA tag to docker build image
2021-01-29 20:22:45 -07:00
30277188db
[CICD] Checking master branch in change_detect
2021-01-29 12:58:53 -07:00
bdf03c8b26
Bug fix on Docker build and upload on master ( #202 )
...
* [CI/CD] Added force master image update option
* [CI/CD] Fixed .dockerignore while master image building
* [Test] checking correctness of source_modified flag
* [Bugfix] Fixed openfpga_flow in dockerignore
* [CICD] Added more context in dockerignore
* [CICD] Updated Dockerfile.master
* [CICD] Reverted test variables
2021-01-29 11:16:57 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
tangxifan
Awais Abbas
nadeemyaseen-rs
nadeemyaseen-rs
Ganesh Gore
coolbreeze413
Maciej Kurc
AurelienAlacchi