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[Arch] Bug fix in DSP with registers architecture

This commit is contained in:
tangxifan 2022-01-02 20:34:26 -08:00
parent 9c476ed5db
commit f667065f75
1 changed files with 4 additions and 2 deletions
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6
openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
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@ -376,9 +376,11 @@
</direct>
<mux name="b2b" input="mult_8x8_slice.B_cfg ff_b.Q" output="mult_8x8.B">
</mux>
<direct name="a2ff" input="mult_8x8_slice.B_cfg" output="ff_B.D">
<direct name="b2ff" input="mult_8x8_slice.B_cfg" output="ff_B.D">
</direct>
<direct name="out2out" input="mult_8x8.Y" output="mult_8x8_slice.OUT_cfg">
<mux name="out2out" input="mult_8x8.Y ff_Y.Q" output="mult_8x8_slice.OUT_cfg">
</mux>
<direct name="out2ff" input="mult_8x8.Y" output="ff_Y.D">
</direct>
<complete name="clk_ff_A" input="mult_8x8.clk" output="ff_A.clk"/>
<complete name="clk_ff_B" input="mult_8x8.clk" output="ff_B.clk"/>