From f667065f7502de259d0b45add247322fca248645 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 2 Jan 2022 20:34:26 -0800
Subject: [PATCH] [Arch] Bug fix in DSP with registers architecture

---
 openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
index 3edd0e4f0..d7e9028d5 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
@@ -376,9 +376,11 @@
             </direct>
             <mux name="b2b" input="mult_8x8_slice.B_cfg ff_b.Q" output="mult_8x8.B">
             </mux>
-            <direct name="a2ff" input="mult_8x8_slice.B_cfg" output="ff_B.D">
+            <direct name="b2ff" input="mult_8x8_slice.B_cfg" output="ff_B.D">
             </direct>
-            <direct name="out2out" input="mult_8x8.Y" output="mult_8x8_slice.OUT_cfg">
+            <mux name="out2out" input="mult_8x8.Y ff_Y.Q" output="mult_8x8_slice.OUT_cfg">
+            </mux>
+            <direct name="out2ff" input="mult_8x8.Y" output="ff_Y.D">
             </direct>
             <complete name="clk_ff_A" input="mult_8x8.clk" output="ff_A.clk"/>
             <complete name="clk_ff_B" input="mult_8x8.clk" output="ff_B.clk"/>